SimCom SIM5215 Hardware Design page 49

AUX_PCM_DIN setup time before falling
T(suauxdin)
edge of AUX_PCM_CLK
AUX_PCM_DIN hold time after falling edge
T(hauxdin)
of AUX_PCM_CLK
Delay
T(pauxdout)
AUX_PCM_DOUT valid
*Note: T(auxclk) = 1/(128 KHz).
Primary PCM (2048 KHz PCM clock)
SIM5215&SIM5216 also supports 2.048 MHz PCM data and sync timing for υ -law codec. This is called
the primary PCM interface. User can use AT command to take the mode you want as discussed above.
SIM5215&SIM5216_Hardware Design_V2.02
from AUX_PCM_CLK
Figure 37: Synchrony timing
Figure 38: EXT CODEC to MODULE timing
Figure 39: MODULE to EXT CODEC timing
Smart Machine Smart Decision
70
20
rising to
–
49
– – ns
– – ns
– 50 ns
2012-08-31