3. SCHEMATICS AND LAYOUT
Hardware Controls
Optical S/PDIF
Input
Coaxial S/PDIF
Receiver
Input
Figure 3
Direct External
Input
+5V Input, +3.3V Regulator
Figure 3
CS8416
VL Select:
Manual
5V or 3.3V
Reset
CS8416
S/PDIF
Clocks &
Serial
Data
Audio
Selection
Clocks &
(Headers)
Data
Figure 3
Figure 2. System Block Diagram and Signal Flow
Power:
Figure 4
CS4354
De-emphasis
Select
Serial
Audio
Clocks &
CS4354
Data
Figure 3
Indicator LEDs
+5V power
+3.3V power
VL power
S/PDIF Error
Figure 3
AOUTA
Filter
Analog
Figure 3
Outputs
AOUTB
Filter
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