Texas Instruments TSB12LV26 Data Manual
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Texas Instruments TSB12LV26 Data Manual

Texas Instruments TSB12LV26 Data Manual

Ohci-lynx pci-based ieee 1394 host controller
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TSB12LV26
OHCI Lynx PCI Based IEEE 1394 Host Controller
Data Manual
2000
Bus Solutions

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Summary of Contents for Texas Instruments TSB12LV26

  • Page 1 TSB12LV26 OHCI Lynx PCI Based IEEE 1394 Host Controller Data Manual 2000 Bus Solutions...
  • Page 2 Printed in U.S.A., 03/00 SLLS366A...
  • Page 3 TSB12LV26 OHCI-Lynx PCI-Based IEEE 1394 Host Controller Data Manual Literature Number: SLLS366A March 2000 Printed on Recycled Paper...
  • Page 4 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability.

  • Page 5: Table Of Contents

    ..........TSB12LV26 Controller Programming Model...
  • Page 6 Configuration ROM Header Register Bus Identification Register Bus Options Register 4.10 GUID High Register 4.11 GUID Low Register 4.12 Configuration ROM Mapping Register 4.13 Posted Write Address Low Register 4.14 Posted Write Address High Register 4.15 Vendor ID Register 4.16 Host Controller Control Register 4.17 Self-ID Buffer Pointer Register...
  • Page 7 Switching Characteristics for PHY-Link Interface Mechanical Information ..........

  • Page 8: List Of Illustrations

    Figure 2–1 Terminal Assignments 3–1 TSB12LV26 Block Diagram 5–1 GPIO2 and GPIO3 Logic Diagram List of Illustrations Title ......... . .

  • Page 9: List Of Tables

    List of Tables Table 2–1 Signals Sorted by Terminal Number 2–2 Signal Names Sorted Alphanumerically to Terminal Number 2–3 Power Supply Terminals ......... 2–4 PCI System Terminals .
  • Page 10 4–10 Host Controller Control Register Description 4–11 Self-ID Count Register Description 4–12 Isochronous Receive Channel Mask High Register Description 4–13 Isochronous Receive Channel Mask Low Register Description 4–14 Interrupt Event Register Description 4–15 Interrupt Mask Register Description 4–16 Isochronous Transmit Interrupt Event Register Description 4–17 Isochronous Receive Interrupt Event Register Description 4–18 Fairness Control Register Description 4–19 Link Control Register Description...

  • Page 11: Introduction

    1 Introduction 1.1 Description The Texas Instruments TSB12LV26 is a PCI-to-1394 host controller compatible with the latest PCI Local Bus , PCI Bus Power Management Interface , IEEE 1394-1995, and 1394 Open Host Controller Interface Specification . The chip provides the IEEE 1394 link function, and is compatible with serial bus data rates of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.

  • Page 12: Related Documents

    PC 99 Design Guide PCI Bus Power Management Interface Specification (Revision 1.0) PCI Local Bus Specification (Revision 2.2) Serial Bus Protocol 2 (SBP–2) 1.4 Ordering Information ORDERING NUMBER TSB12LV26 OHCI-Lynx PCI-Based IEEE 1394 Host Controller 1–2 NAME VOLTAGE 3.3V-, 5V-Tolerant I/Os...

  • Page 13: Terminal Descriptions

    2 Terminal Descriptions This section provides the terminal descriptions for the TSB12LV26. Figure 2–1 shows the signal assigned to each terminal in the package. Table 2–1 is a listing of signal names arranged in terminal number order, and Table 2–2 lists terminals in alphanumeric order by signal names.

  • Page 14: Signals Sorted By Terminal Number

    Table 2–1. Signals Sorted by Terminal Number TERMINAL NAME GPIO2 GPIO3 V CCP PCI_CLKRUN PCI_INTA 3.3 V CC G_RST PCI_CLK 3.3 V CC PCI_GNT PCI_REQ V CCP PCI_PME PCI_AD31 PCI_AD30 3.3 V CC PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 2–2 TERMINAL NAME TERMINAL NAME PCI_AD25 PCI_SERR...

  • Page 15: Signal Names Sorted Alphanumerically To Terminal Number

    Table 2–2. Signal Names Sorted Alphanumerically to Terminal Number TERMINAL NAME TERMINAL NAME CYCLEIN PCI_AD11 CYCLEOUT PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 GPIO2 PCI_AD22 GPIO3 PCI_AD23 G_RST PCI_AD24 PCI_AD0 PCI_AD25 PCI_AD1 PCI_AD26 PCI_AD2 PCI_AD27 PCI_AD3 PCI_AD28 PCI_AD4 PCI_AD29 PCI_AD5...

  • Page 16: Pci System Terminals

    PCI_INTA as open-drain. PCI reset. When this bus reset is asserted, the TSB12LV26 places all output buffers in a high impedance state and resets all internal registers except device power management context- and vendor-specific bits initialized by host power-on software. When PCI_RST is asserted, the device is completely nonfunctional.

  • Page 17: Pci Address And Data Terminals

    Table 2–5. PCI Address and Data Terminals TERMINAL NAME PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the PCI interface. PCI_AD16 During the address phase of a PCI cycle, AD31–AD0 contain a 32-bit address or other destination information.

  • Page 18: Pci Interface Control Terminals

    When PCI_FRAME is deasserted, the PCI bus transaction is in the final data phase. PCI bus grant. This signal is driven by the PCI bus arbiter to grant the TSB12LV26 access to the PCI bus after PCI_GNT the current data transaction has completed.

  • Page 19: Ieee 1394 Phy/Link Terminals

    PHY_LPS required. PHY_LREQ Link request. This signal is driven by the TSB12LV26 to initiate a request for the PHY to perform some service. PHY_SCLK System clock. This input from the PHY provides a 49.152-MHz clock signal for data synchronization. TERMINAL...
  • Page 20 2–8...

  • Page 21: Tsb12Lv26 Controller Programming Model

    3 TSB12LV26 Controller Programming Model This section describes the internal registers used to program the TSB12LV26. All registers are detailed in the same format: a brief description for each register, followed by the register offset and a bit table describing the reset state for each register.
  • Page 22 Generator & Access Cycle Monitor & Status Monitor Synthesized Request Bus Reset Filters General Request Receive Receive Async Response FIFO Receive ISO Receive Contexts Figure 3–1. TSB12LV26 Block Diagram Serial GPIOs MISC Interface Link Transmit PHY / Link Interface Link Receive...

  • Page 23: Pci Configuration Registers

    3.1 PCI Configuration Registers The TSB12LV26 is a single-function PCI device. The configuration header is compliant with the PCI Local Bus Specification as a standard header. Table 3–2 illustrates the PCI configuration header that includes both the predefined portion of the configuration space and the user definable registers.

  • Page 24: Device Id Register

    8020h 3.4 Command Register The command register provides control over the TSB12LV26 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification , as seen in the bit descriptions of Table 3–3.

  • Page 25: Status Register

    Signaled system error. This bit is set when PCI_SERR is enabled and the TSB12LV26 has signaled a SYS_ERR system error to the host. Received master abort. This bit is set when a cycle initiated by the TSB12LV26 on the PCI bus has been MABORT terminated by a master abort.

  • Page 26: Class Code And Revision Id Register

    3.6 Class Code and Revision ID Register The class code and revision ID register categorizes the TSB12LV26 as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the least significant byte.

  • Page 27: Header Type And Bist Register

    3.8 Header Type and BIST Register The header type and BIST register indicates the TSB12LV26 PCI header type, and indicates no built-in self test. See Table 3–7 for a complete description of the register contents. Name Type Default Register: Header type and BIST...

  • Page 28: Ti Extension Base Address Register

    3.10 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory-mapped TI extension registers. See the OHCI Base Address Register , Section 3.9, for bit field details. Name Type Default Name Type Default...

  • Page 29: Power Management Capabilities Pointer Register

    0100h Table 3–10. Interrupt Line and Pin Register Description FIELD NAME TYPE Interrupt pin. Returns 01h when read, indicating that the TSB12LV26 PCI function signals interrupts on 15–8 INTR_PIN the PCI_INTA pin. Interrupt line. This field is programmed by the system and indicates to software which interrupt line the 7–0...

  • Page 30: Min_Gnt And Max_Lat Register

    ROM. Minimum grant. The contents of this register may be used by host BIOS to assign a latency timer and class cache line size register (offset 0Ch, see Section 3.7) value to the TSB12LV26. The default for this register 7–0 MIN_GNT indicates that the TSB12LV26 may need to sustain burst transfers for nearly 64 s;...

  • Page 31: Capability Id And Next Item Pointer Register

    Table 3–13. Capability ID and Next Item Pointer Register Description FIELD NAME TYPE Next item pointer. The TSB12LV26 supports only one additional capability that is communicated to 15–8 NEXT_ITEM the system through the extended capabilities list; thus, this field returns 00h when read.

  • Page 32: Power Management Capabilities Register

    FIELD NAME TYPE PCI_PME support from D3 cold . When this bit is set, the TSB12LV26 generates a PCI_PME wake event from D3 cold . This bit state is dependent upon the TSB12LV26 V AUX implementation and may be PME_D3COLD configured by host software using bit 15 (PME_D3COLD) in the PCI miscellaneous configuration register (see Section 3.20).

  • Page 33: Power Management Control And Status Register

    3.19 Power Management Extension Register The power management extension register provides extended power management features not applicable to the TSB12LV26, thus it is read-only and returns 0s when read. See Table 3–16 for a complete description of the register contents.

  • Page 34: Miscellaneous Configuration Register

    (offset 46h, see Section 3.17). If wake from the D2 power state implemented in the TSB12LV26 is not desired, then this bit may be cleared to indicate to power management software that wake-up from D2 is not supported.

  • Page 35: Link Enhancement Control Register

    It is recommended that this bit be set to 1. This bit is not assigned in the TSB12LV26 follow-on products since this bit location loaded by the serial RSVD ROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the host controller control register (OHCI offset 50h/54h, see Section 4.16).

  • Page 36: Subsystem Access Register

    Table 3–18. Link Enhancement Control Register Description (Continued) FIELD NAME TYPE Enable acceleration enhancements. OHCI-Lynx compatible. When set to 1, this bit notifies the PHY enab_accel that the link supports the 1394a acceleration enhancements, i.e., ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1. RSVD Reserved.

  • Page 37: Gpio Control Register

    Table 3–20. GPIO Control Register Description FIELD NAME TYPE When this bit is set, a TSB12LV26 general-purpose interrupt event occurs on a level change of the GPIO3 input. This event may generate an interrupt, with mask and event status reported through the INT_3EN OHCI interrupt mask (OHCI offset 88h/8Ch, see Section 4.22) and interrupt event (OHCI offset...
  • Page 38 3–18...

  • Page 39: Ohci Registers

    2-Kbyte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 3.9). These registers are the primary interface for controlling the TSB12LV26 IEEE 1394 link function. This section provides the register interface and bit descriptions. There are several set/clear register pairs in this programming model, which are implemented to solve various issues with typical read-modify-write control registers.
  • Page 40 Table 4–1. OHCI Register Map (Continued) DMA CONTEXT Self ID Reserved Self ID buffer Self ID count Reserved — Isochronous receive channel mask high Isochronous receive channel mask high Isochronous receive channel mask low Isochronous receive channel mask low Interrupt event Interrupt event Interrupt mask Interrupt mask...
  • Page 41 Table 4–1. OHCI Register Map (Continued) DMA CONTEXT REGISTER NAME Asynchronous context control Asynchronous context control Asychronous Asychronous Request Transmit Reserved [ ATRQ ] Asynchronous context command pointer Reserved Asynchronous context control Asynchronous context control Asychronous Asychronous Reserved Response Transmit [ ATRS ] Asynchronous context command pointer Reserved...

  • Page 42: Ohci Version Register

    31–25 RSVD Reserved. Bits 31–25 return 0s when read. The TSB12LV26 sets this bit if the serial ROM is detected. If the serial ROM is present, then the GUID_ROM Bus_Info_Block is automatically loaded on hardware reset. Major version of the OHCI. The TSB12LV26 is compliant with the 1394 Open Host Controller Interface 23–16...

  • Page 43: Guid Rom Register

    Software sets this bit to reset the GUID ROM address to 0. When the TSB12LV26 completes the reset, addrReset it clears this bit. The TSB12LV26 does not automatically fill bits 23–16 (rdData field) with the 0 th byte. 30–26 RSVD Reserved.

  • Page 44: Asynchronous Transmit Retries Register

    4.3 Asynchronous Transmit Retries Register The asynchronous transmit retries register indicates the number of times the TSB12LV26 attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 4–4 for a complete description of the register contents.

  • Page 45: Csr Compare Register

    Default: 8000 000Xh Table 4–5. CSR Control Register Description FIELD NAME TYPE This bit is set by the TSB12LV26 when a compare-swap operation is complete. It is cleared whenever csrDone this register is written. 30–2 RSVD Reserved. Bits 30–2 return 0s when read.

  • Page 46: Bus Identification Register

    4.7 Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset FFFF F000 0400h. See Table 4–6 for a complete description of the register contents. Name Type Default Name Type Default Register:...

  • Page 47: Bus Options Register

    4.9 Bus Options Register The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 4–7 for a complete description of the register contents. Name Type Default Name Type Default Register: Bus options Type: Read/Write, Read-only Offset: Default: X0XX A0X2h...

  • Page 48: Guid High Register

    4.10 GUID High Register The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0s on a hardware reset, which is an illegal GUID value. If a serial ROM is detected, then the contents of this register are loaded through the serial ROM interface after a PCI reset.

  • Page 49: Posted Write Address Low Register

    4.12 Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. See Table 4–8 for a complete description of the register contents. Name Type Default...

  • Page 50: Vendor Id Register

    4.15 Vendor ID Register The vendor ID register holds the company ID of an organization that specifies any vendor-unique registers. The TSB12LV26 does not implement Texas Instruments unique behavior with regards to OHCI. Thus, this register is read-only and returns 0s when read.

  • Page 51: Host Controller Control Register

    When this bit is set, all TSB12LV26 states are reset, all FIFOs are flushed, and all OHCI registers are set to their hardware reset values unless otherwise specified. PCI registers are not affected by this bit.

  • Page 52: Self-Id Buffer Pointer Register

    4.17 Self-ID Buffer Pointer Register The self-ID buffer pointer register points to the 2-Kbyte aligned base address of the buffer in host memory where the self-ID packets are stored during bus initialization. Bits 31–11 are read/write accessible. Reserved bits 10–0 are read-only and return 0s when read.

  • Page 53: Isochronous Receive Channel Mask High Register

    Table 4–12. Isochronous Receive Channel Mask High Register Description FIELD NAME TYPE isoChannel63 When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 63. isoChannel62 When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 62. isoChannel61 When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 61.

  • Page 54: Isochronous Receive Channel Mask Low Register

    Table 4–12. Isochronous Receive Channel Mask High Register Description (Continued) FIELD NAME TYPE isoChannel38 When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 38. isoChannel37 When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 37. isoChannel36 When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 36.

  • Page 55: Interrupt Event Register

    3.23). 29–27 RSVD Reserved. Bits 29–27 return 0s when read. The TSB12LV26 has received a PHY register data byte which can be read from the PHY layer control phyRegRcvd RSCU register (OHCI offset ECh, see Section 4.30). If bit 21 (cycleMaster) of the link control register (OHCI offset E0h/E4h, see Section 4.28) is set, then...
  • Page 56 This bit is turned off simultaneously when bit 17 (busReset) is turned on. Reserved. Bits 15–10 return 0s when read. Indicates that the TSB12LV26 sent a lock response for a lock request to a serial bus register, but did not receive an ack_complete.

  • Page 57: Interrupt Mask Register

    (bit 31) and VendorSpecific (bit 30), the enables for each interrupt event align with the interrupt event register bits detailed in Table 4–14. See Table 4–15 for a description of bits 31 and 30. This register is fully compliant with OHCI and the TSB12LV26 adds an OHCI 1.0 compliant interrupt function to bit 30. Name...

  • Page 58: Isochronous Transmit Interrupt Event Register

    4.23 Isochronous Transmit Interrupt Event Register The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command completes and its interrupt bits are set. Upon determining that the interrupt event register (OHCI offset 80h/84h, see Section 4.21) isochTx (bit 6) interrupt has occurred, software can check this register to determine which context(s) caused the interrupt.

  • Page 59: Isochronous Transmit Interrupt Mask Register

    4.24 Isochronous Transmit Interrupt Mask Register The isochronous transmit interrupt mask set/clear register is used to enable the isochTx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register.

  • Page 60: Isochronous Receive Interrupt Event Register

    4.25 Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set. Upon determining that the interrupt event register (OHCI offset 80h/84h, see Section 4.21) isochRx (bit 7) interrupt has occurred, software can check this register to determine which context(s) caused the interrupt.

  • Page 61: Fairness Control Register

    4.27 Fairness Control Register The fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. See Table 4–18 for a complete description of the register contents. Name Type Default Name...

  • Page 62: Link Control Register

    The link control set/clear register provides the control flags that enable and configure the link core protocol portions of the TSB12LV26. It contains controls for the receiver and cycle timer. See Table 4–19 for a complete description of the register contents.

  • Page 63: Node Identification Register

    FIELD NAME TYPE This bit indicates whether or not the TSB12LV26 has a valid node number. It is cleared when a 1394 bus iDValid reset is detected and set when the TSB12LV26 receives a new node number from the PHY.

  • Page 64: Phy Layer Control Register

    Table 4–21. PHY Control Register Description FIELD NAME TYPE This bit is cleared to 0 by the TSB12LV26 when either bit 15 (rdReg) or bit 14 (wrReg) is set. This bit is rdDone set when a register transfer is received from the PHY.

  • Page 65: Isochronous Cycle Timer Register

    The isochronous cycle timer register indicates the current cycle number and offset. When the TSB12LV26 is cycle master, this register is transmitted with the cycle start message. When the TSB12LV26 is not cycle master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference.

  • Page 66: Asynchronous Request Filter High Register

    The node ID comparison is done if the source node is on the same bus as the TSB12LV26. Nonlocal bus sourced packets are not acknowledged unless bit 31 in this register is set.
  • Page 67 If this bit is set for local bus node number 50, then asynchronous requests received by the asynReqResource50 TSB12LV26 from that node are accepted. If this bit is set for local bus node number 49, then asynchronous requests received by the asynReqResource49 TSB12LV26 from that node are accepted.

  • Page 68: Asynchronous Request Filter Low Register

    If this bit is set for local bus node number 31, then asynchronous requests received by the TSB12LV26 from that node are accepted. If this bit is set for local bus node number 30, then asynchronous requests received by the TSB12LV26 from that node are accepted.

  • Page 69: Physical Request Filter High Register

    If this bit is set, then all physical requests received by the TSB12LV26 from non-local bus nodes are accepted. If this bit is set for local bus node number 62, then physical requests received by the TSB12LV26 from that node are handled through the physical request context.
  • Page 70 4–32 DESCRIPTION If this bit is set for local bus node number 51, then physical requests received by the TSB12LV26 from that node are handled through the physical request context. If this bit is set for local bus node number 50, then physical requests received by the TSB12LV26 from that node are handled through the physical request context.

  • Page 71: Physical Request Filter Low Register

    Physical request filter low DESCRIPTION If this bit is set for local bus node number 31, then physical requests received by the TSB12LV26 from that node are handled through the physical request context. If this bit is set for local bus node number 30, then physical requests received by the TSB12LV26 from that node are handled through the physical request context.

  • Page 72: Physical Upper Bound Register (Optional Register)

    4.36 Physical Upper Bound Register (Optional Register) The physical upper bound register is an optional register and is not implemented. It returns all 0s when read. Name Type Default Name Type Default Register: Physical upper bound Type: Read-only Offset: 120h Default: 0000 0000h 4–34...

  • Page 73: Asynchronous Context Control Register

    Software sets this bit to cause the TSB12LV26 to continue or resume descriptor processing. The wake TSB12LV26 clears this bit on every descriptor fetch. The TSB12LV26 sets this bit when it encounters a fatal error and clears the bit when software resets dead bit 15 (run).

  • Page 74: Asynchronous Context Command Pointer Register

    The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the TSB12LV26 accesses when software enables the context by setting the asynchronous context control register (see Section 4.37) bit 15 (run). See Table 4–28 for a complete description of the register contents.

  • Page 75: Isochronous Transmit Context Control Register

    Software sets this bit to cause the TSB12LV26 to continue or resume descriptor processing. The wake TSB12LV26 clears this bit on every descriptor fetch. The TSB12LV26 sets this bit when it encounters a fatal error and clears the bit when software resets dead bit 15 (run).

  • Page 76: Isochronous Transmit Context Command Pointer Register

    The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the TSB12LV26 accesses when software enables an isochronous transmit context by setting the isochronous transmit context control register (see Section 4.39) bit 15 (run). The n value in the following register...
  • Page 77 Software sets this bit to cause the TSB12LV26 to continue or resume descriptor processing. The wake TSB12LV26 clears this bit on every descriptor fetch. The TSB12LV26 sets this bit when it encounters a fatal error and clears the bit when software resets dead bit 15 (run).

  • Page 78: Isochronous Receive Context Command Pointer Register

    The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the TSB12LV26 accesses when software enables an isochronous receive context by setting the isochronous receive context control register (see Section 4.41) bit 15 (run). The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3).

  • Page 79: Isochronous Receive Context Match Register

    4.43 Isochronous Receive Context Match Register The isochronous receive context match register is used to start an isochronous receive context running on a specified cycle number, to filter incoming isochronous packets based on tag values, and to wait for packets with a specified sync value.
  • Page 80 4–42...

  • Page 81: Gpio Interface

    5 GPIO Interface The general-purpose input/output (GPIO) interface consists of two GPIO ports. GPIO2 and GPIO3 power up as general-purpose inputs and are programmable via the GPIO control register. Figure 5–1 shows the logic diagram for GPIO2 and GPIO3 implementation. GPIO Read Data GPIO Write Data GPIO_Invert...
  • Page 82 5–2...

  • Page 83: Serial Rom Interface

    6 Serial ROM Interface The TSB12LV26 provides a serial bus interface to initialize the 1394 global unique ID register and a few PCI configuration registers through a serial ROM. The TSB12LV26 communicates with the serial ROM via the 2-wire serial interface.
  • Page 84 BYTE ADDRESS PCI maximum latency (0h) Link_enhancement- HCControl. Control.enab_unfair ProgramPhy Enable [15] [14] RSVD RSVD RSVD RSVD [15] [14] PME D3 Cold RSVD RSVD RSVD 15–1E 6–2 Table 6–2. Serial ROM Map BYTE DESCRIPTION PCI_minimum grant (0h) PCI vendor ID PCI vendor ID (msbyte) PCI subsystem ID (lsbyte) PCI subsystem ID...

  • Page 85: Absolute Maximum Ratings Over Operating Temperature Ranges

    7 Electrical Characteristics 7.1 Absolute Maximum Ratings Over Operating Temperature Ranges Supply voltage range, V ............Supply voltage range, V .

  • Page 86: Recommended Operating Conditions

    7.2 Recommended Operating Conditions V CC Core voltage V CCP V CCP PCI I/O clamping voltage PCI I/O clamping voltage V IH † V IH † † High-level input voltage High level input voltage V IL † V IL † †...

  • Page 87: Electrical Characteristics Over Recommended Operating Conditions

    7.3 Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) V OH High-level output voltage V OL † † † Low-level output voltage I OZ 3-state output high-impedance I IL I IL Low-level input current Low level input current I IH I IH High level input current High-level input current...
  • Page 88 7–4...

  • Page 89: Mechanical Information

    8 Mechanical Information The TSB12LV26 is packaged in a 100-terminal PZ package. The following shows the mechanical dimensions for the PZ package. PZ (S-PQFP-G100) 0,50 12,00 TYP 14,20 13,80 16,20 15,80 1,45 1,35 1,60 MAX NOTES: A. All linear dimensions are in millimeters.
  • Page 90 8–2...
  • Page 91 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability.

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