Jumpers; Surface-Mount Jumpers - Texas Instruments ADS61B23EVM User Manual

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Description
Parallel mode: SEN pin
voltage bias
SEN control
ADC control mode
Parallel mode: SCLK pin
voltage bias
ADS61xx/ADS61B23
power down
SDATA control
SCLK control
Description
Clock input path selection
Clock input path selection
Clock input path selection
Analog input path
Analog input path
THS4509 power down
CDCP1803 power down
SLAU206B – September 2007 – Revised April 2008
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Table 2. Jumpers
Reference Designator
J1 5–6, Offset binary, CMOS output
J2 2–3, EVM controlled
J3 2–3, Parallel mode
J4 1–2, 0-dB Gain, Int Ref
J5 1–2, ADS61xx/ADS61B23 powered on
J6 1–2, USB or FPGA controlled
J7 2–3, EVM controlled
Table 3. Surface-Mount Jumpers
Reference Designator
JP1 Probe point for CDCP1803 output
JP2 1–2, transformer coupled path
JP3 1–2, transformer coupled path
JP4 1–2, transformer coupled path
JP5 1–2, transformer coupled input path
JP6 1–2, transformer coupled input path
JP7 2–3, THS4509 powered down
JP8 2–3, CDCP1803 powered down
Default Selection
Default Selection
Circuit Description
Optional Selection
Multiple choices
1–2, USB or FPGA
controlled
1–2, serial mode
Multiple choices
2–3, ADS61xx/ADS61B23
powered off
2–3, EVM controlled
2–3, USB or FPGA
controlled
Optional Selection
2–3, CDCP1803 path
2–3, CDCP1803 path
2–3, CDCP1803 path
2–3, THS4509 path
2–3, THS4509 path
1–2, THS4509 powered
on
1–2, CDCP1803 powered
on
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