Texas Instruments ADS61B23EVM User Manual page 7

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Note that the THS4509 used on this EVM is pinout compatible with the THS4508, THS4511, THS4513,
and THS4520. Users can easily interchange the amplifier on this EVM and pick the appropriate amplifier
based on common-mode range, power supplies, and frequency of operation. Contact your local Texas
Instruments (TI) sales representative for assistance in selection of these amplifiers.
2.2.4 ADC Clock Input
Connect a filtered, low-phase-noise clock input to J9. A transformer, T3, provides the conversion from a
single-ended clock signal into a differential clock signal.
The EVM also provides a clock distribution path using the CDCP1803. The CDCP1803 provides for a 1:3
LVDS fanout helpful when clocking multiple ADCs from the same clocking source. Users selecting this
input path should use a low-jitter square-wave input. In addition, the CDCP1803 jitter performance makes
this a valid clocking solution only for input frequencies in the first Nyquist zone, as jitter degrades SNR for
frequencies much above the first Nyquist zone. To use this path, change jumper JP8 to short 1–2, and
JP2, JP3, and JP4 to short pins 2–3.
2.2.5 ADC Digital Outputs
The ADS61xx/ADS61B23 ADC parallel digital outputs are brought to J10, a high-density Samtec™
connector. Several options are available in processing the ADC data.
1. The mating logic analyzer breakout board can capture the ADC data using a logic analyzer. Users who
choose this option should use the companion breakout board and
Users lacking access to a logic analyzer can use the TSW1100 to capture the digital data. See the
connection guidelines in
2. Users can create their own digital interface board which directly interfaces to the ADC. In this case,
they design their mating digital interface board with the Samtec part number QSO-060-01-F-D-A, which
is the companion part number to the EVM connector.
SLAU206B – September 2007 – Revised April 2008
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Section 4.1.
Circuit Description
Table 1 for the connection details.
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