Circuit Description; Schematic Diagram; Adc Circuit Function - Texas Instruments ADS61B23EVM User Manual

Circuit Description

2 Circuit Description
2.1

Schematic Diagram

The schematic diagram for the EVM is in
2.2

ADC Circuit Function

The following sections describe the function of individual circuits. See the relevant data sheet for device
operating characteristics.
2.2.1 ADC Operational Mode
By default, the ADC is configured to operate in parallel-mode operation, because jumper (J3) asserts a
3.3-V state to the ADC reset pin. Consequently, the SW1 reset pushbutton must be pressed only when the
device is configured in serial operation mode. Because the ADC is in parallel operation mode, voltages
are used to set the ADC configuration modes. Users can use the EVM silkscreen to set the operation
modes.
2.2.2 EVM Power Connections
Power is supplied to the EVM by banana jack sockets. Separate connections are provided for a 3.3-V
digital buffer supply (J11) and 3.3-V analog supply (J13); however, by default these are shorted together
using R65, a 0- resistor. Consequently, users can supply power to either J11 or J13 to power the ADC.
The separate connections allow users to separate analog and digital supplies by removing R65. When
using the amplifier evaluation path, connect the positive rail to J20 and the negative rail to J16. The
voltages depend on the coupling method and connection to the ADC. If the ADC VCM is not supplied to
the amplifier and the amplifier is connected to the ADC in a dc-coupled fashion, set J20 to 4 V and J16 to
–1 V. In ac-coupled configurations where the ADC VCM biases the ADC inputs, connect J20 to 5 V and
J16 to GND. The ADC SPI interface and
to 5 V for operation of those circuits.
2.2.3 ADC Analog Inputs
The EVM is configured to accept a single-ended input source and convert it to an ac-coupled differential
signal using a transformer. The inputs to the ADC must be dc-biased, which is accomplished by using the
ADC VCM output. The input is provided by the SMA connector J8.
Using SMA input J10, users can evaluate the ADC using a
single-ended input into a differential signal while providing 10 dB of signal gain. Users should enable the
amplifier path by connecting JP7 1–2 and by shorting positions 2–3 on both surface-mount jumpers JP5
and JP6. At low input frequencies, the ADC represents a high-input impedance and R38, R46, and C76
form a low-pass filter with a 3-db cutoff frequency of 70 MHz. Users can change these component values
depending on the bandwidth of the signal they are digitizing to band-limit the input noise into the ADC.
Using an excessively high cutoff frequency degrades the SNR of the system. Before beginning evaluation
of the amplifier path, a user must choose whether to dc-couple or ac-couple the amplifier path.
In a dc-coupled system, replace C75 and C77 with 0-
VCM to set the CM input of the amplifier by ensuring that R21 is populated with a 0-
the ADC has a common-mode voltage of 1.5 V and because the THS4509 is not a rail-to-rail amplifier,
adjust VCC to 4 V and –VCC to –1 V, which can be done by applying the respective voltages to J20 and
J16.
For an ac-coupled system, use the voltage divider R37 and R45 to set the common-mode input of the
amplifier, which should be set to the midpoint of the amplifier supply. Alternatively, users can leave R37
and R45 unpopulated and the amplifier sets its own common voltage to (VCC – VEE)/2. Capacitors C75
and C77 provide ac-coupling of the system, and the ADC inputs then can be biased by the R41 and R42
combination. Another ac-coupled approach, not supported on this EVM, is to use a transformer at the
outputs of the THS4509. In this case, the transformer provides for ac-coupling, and the inputs of the ADC
can be biased by feeding the ADC VCM to the transformer center tap on the secondary.
6
Section 6.3.
CDCP1803 also are powered through J20, which should be set
THS4509
resistors and remove R37 and R45. Use the ADC
amplifier, which converts a
resistor. Because
SLAU206B – September 2007 – Revised April 2008
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