Table 5. Post Progress Codes - Intel S9200WK Series Setup And Service Manual

Intel® Server System S9200WK Product Family Setup and Service Guide
BIOS POST Progress Codes
The following table provides a list of all POST progress codes.
Diagnostic LED Decoder
1 = LED On, 0 = LED Off
Upper Nibble
Checkpoint
(Amber - Read 1st)
MSB
8h 4h
SEC Phase
01h 0 0
02h 0 0
03h 0 0
04h 0 0
05h 0 0
06h 0 0
UPI RC (Fully leverage without platform change)
A1h 1 0
A3h 1 0
A7h 1 0
A8h 1 0
A9h 1 0
AAh 1 0
ABh 1 0
ACh 1 0
ADh 1 0
AEh 1 0
AFh 1 0
07h 0 0
08h 0 0
09h 0 0
0Eh 0 0
0Fh 0 0
PEI Phase
10h 0 0
11h 0 0
15h 0 0
19h 0 0
MRC Progress Codes
31h 0 0
32h 0 0
33h 0 0
4Fh 0 1
DXE Phase
60h 0 1
61h 0 1
62h 0 1
63h 0 1
65h 0 1

Table 5. POST progress codes

Lower Nibble
(Green - Read 2nd)
LSB
2h 1h 8h 4h 2h 1h
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 0 1 1
0 0 0 1 0 0
0 0 0 1 0 1
0 0 0 1 1 0
1 0 0 0 0 1
1 0 0 0 1 1
1 0 0 1 1 1
1 0 1 0 0 0
1 0 1 0 0 1
1 0 1 0 1 0
1 0 1 0 1 1
1 0 1 1 0 0
1 0 1 1 0 1
1 0 1 1 1 0
1 0 1 1 1 1
0 0 0 1 1 1
0 0 1 0 0 0
0 0 1 0 0 1
0 0 1 1 1 0
0 0 1 1 1 1
0 1 0 0 0 0
0 1 0 0 0 1
0 1 0 1 0 1
0 1 1 0 0 1
1 1 0 0 0 1
1 1 0 0 1 0
1 1 0 0 1 1
0 0 1 1 1 1
1 0 0 0 0 0
1 0 0 0 0 1
1 0 0 0 1 0
1 0 0 0 1 1
1 0 0 1 0 1
Description
First POST code after CPU reset
Microcode load begin
CRAM initialization begin
EI Cache When Disabled
SEC Core at Power on Begin
Early CPU initialization during Sec Phase.
Collect info such as SBSP, Boot Mode, Reset type etc.
Setup minimum path between SBSP & other sockets
Topology discovery and route calculation
Program final route
Program final IO SAD setting
Protocol layer and other uncore settings
Transition links to full speed operation
Phy layer setting
Link layer settings
Coherency settings
UPI initialization done
Early SB initialization during Sec Phase.
Early NB initialization during Sec Phase.
End Of Sec Phase.
Microcode Not Found.
Microcode Not Loaded.
PEI Core
CPU PEIM
NB PEIM
SB PEIM
Memory Installed
CPU PEIM (CPU Init)
CPU PEIM (Cache Init)
Dxe IPL started
DXE Core started
DXE NVRAM Init
DXE Setup Init
DXE CPU Init
DXE CPU BSP Select
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