Spi Control Interface Mode - Silicon Laboratories Si4704 Series Programming Manual

AN332

6.3. SPI Control Interface Mode

Figures 9 and 10 show the SPI Control Interface Read and Write Timing Parameters and Diagrams, respectively.
Refer to the Si471x data sheet for timing parameter values.
70%
SCLK
30%
70%
SEN
30%
70%
SDIO
30%
Figure 9. SPI Control Interface Write Timing Parameters
70%
SCLK
30%
70%
SEN
30%
SDIO
70%
or
GPO1
30%
Figure 10. SPI Control Interface Read Timing Parameters
SPI bus mode uses the SCLK, SDIO and SEN pins for read/write operations. The system controller can choose to
receive read data from the device on either SDIO or GPO1. A transaction begins when the system controller drives
SEN = 0. The system controller then pulses SCLK eight times, while driving an 8-bit control byte serially on SDIO.
The device captures the data on rising edges of SCLK. The control byte must have one of five values:
0x48 = write a command (controller drives 8 additional bytes on SDIO)
0x80 = read a response (device drives one additional byte on SDIO)
0xC0 = read a response (device drives 16 additional bytes on SDIO)
0xA0 = read a response (device drives one additional byte on GPO1)
0xE0 = read a response (device drives 16 additional bytes on GPO1)
For write operations, the system controller must drive exactly 8 data bytes (a command and arguments) on SDIO
after the control byte. The data is captured by the device on the rising edge of SCLK.
174
t
HIGH
t
S
t
S
C7 C6–C1 C0
Control Byte In
t
S
t
S
C7 C6–C1
Control Byte In
Confidential Rev. 0.2
t t
LOW HSDIO
D7 D6–D1
8 Data Bytes In
t
CDV
t
HSDIO
C0 D7 D6–D1
16 Data Bytes Out
Bus
Turnaround
t
HSEN
D0
t
HSEN
t
CDZ
D0