Silicon Laboratories Si4704 Series Programming Manual page 169

SCLK
A6-A0,
SDIO
START ADDRESS + R/W
Figure 6. 2-wire Control Interface Read and Write Timing Diagram
2-wire bus mode uses only the SCLK and SDIO pins for signaling. A transaction begins with the START condition,
which occurs when SDIO falls while SCLK is high. Next, the system controller drives an 8-bit control word serially
on SDIO, which is captured by the device on rising edges of SCLK. The control word consists of a seven-bit device
address followed by a read/write bit (read = 1, write = 0). The device acknowledges the control word by driving
SDIO low on the next falling edge of SCLK.
Although the device responds to only a single device address, this address can be changed with the SEN pin (note
that the SEN pin is not used for signaling in 2-wire mode). When SEN = 0, the seven-bit device address is
0010001b. When SEN = 1, the address is 1100011b.
For write operations, the system controller next sends a data byte on SDIO, which is captured by the device on
rising edges of SCLK. The device acknowledges each data byte by driving SDIO low for one cycle on the next
falling edge of SCLK. The system controller may write up to 8 data bytes in a single 2-wire transaction. The first
byte is a command, and the next seven bytes are arguments. Writing more than 8 bytes results in
unpredictable device behavior.
For read operations, after the device has acknowledged the control byte, it will drive an eight-bit data byte on SDIO,
changing the state of SDIO on the falling edges of SCLK. The system controller acknowledges each data byte by
driving SDIO low for one cycle on the next falling edge of SCLK. If a data byte is not acknowledged by the system
controller, the transaction will end. The system controller may read up to 16 data bytes in a single 2-wire
transaction. These bytes contain the status byte and response data from the device.
A 2-wire transaction ends with the STOP condition, which occurs when SDIO rises while SCLK is high.
Table 21 demonstrates the command and response procedure implemented in the system controller to use the 2-
wire bus mode. In this example the TX_TUNE_FREQ command is demonstrated.
Table 21. Command and Response Procedure - 2-Wire Bus Mode
Action
CMD
ARG1
ARG2
ARG3
STATUS
To send the TX_TUNE_FREQ command and arguments, the system controller sends the START condition,
followed by the 8-bit control word, which consists of a seven-bit device address (0010001b SEN = 0 or 1100011b
SEN = 1) and the write bit (0b) indicated by ADDR+W = 00100010b = 0x22. In this example, SEN = 0 resulting in
the control word ADDR+W = 00100010b = 0x22. If instead SEN = 1, the resulting control word would be
ADDR+W = 11000110b = 0xC6. The device acknowledges the control word by setting SDIO = 0, indicated by
R/W
ACK
Data
0x30 TX_TUNE_FREQ
0x00
0x27 Set Station to 101.1 MHz
0x7E (0x277E = 10110 with 10 kHz step size)
→
0x80 Reply Status. Clear-to-send high.
Confidential Rev. 0.2
D7-D0
DATA ACK
Description
AN332
D7-D0
DATA ACK STOP
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