Hold Bit Status; Program Memory Write-Protection - Omron CPM1 Programming Manual

1-2-2 Hold Bit Status

Caution
!

1-2-3 Program Memory Write-protection

Note When the "startup mode designation" is set to 00 and pin 2 of the CPM2C CPU
Unit's DIP switch is ON, the CPM2C will enter RUN mode automatically, regard-
less of the Programming Console's mode switch setting.
Make the settings shown below to determine whether, when the power supply is
turned on, the Forced Status Hold Bit (SR 25211) and/or IOM Hold Bit
(SR 25212) will retain the status that was in effect when the power was last
turned off, or whether the previous status will be cleared.
The Forced Status Hold Bit (SR 25211) determines whether or not the forced
set/reset status is retained when changing from PROGRAM mode to MONITOR
mode.
The IOM Hold Bit (SR 25212) determines whether or not the status of IR bits and
LR bits is retained when PC operation is started and stopped.
In PCs with capacitor backup, do not use the I/O Hold Bit Status and Forced Sta-
tus Hold Bit Status Bits (DM 6601) when the power to the PC is going to be
turned off longer than the memory backup time of the internal capacitor. If the
memory backup time is exceeded, memory status will be unstable even if the I/O
Hold Bit Status and Forced Status Hold Bit Status Bits are used. Unpredictable
results may occur if operation is attempted with unstable memory status.
Note 1. The memory backup time of the internal capacitor varies with the ambient
temperature, but is 20 days at 25
C. Refer to hardware specifications for
more details.
2. The memory backup time assumes that the internal capacitor is fully
charged before power is turned off. Fulling charging the capacitor requires
that power is supplied to the CPU Unit for at least 15 minutes.
In CPM1, CPM1A, CPM2A, and CPM2C PCs, the program memory can be pro-
tected by setting bits 00 to 03 of DM 6602 to 0. Bits 04 to 07 determine whether
Programming Console messages are displayed in English or Japanese.
Programming Console messages
0: English
1: Japanese
Program memory
0: Not write-protected
1: Write-protected
Default: English displays, not write-protected
Bit
15
DM6601
SR 25211 setting
0: Clear status
1: Retain status
SR 25212 setting
0: Clear status
1: Retain status
Default: Clear both.
Bit
15
DM6602
Section
0
0 0
Always 00
0
0 0
Always 00
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