Processor 7/7 - Clevo W130HU Service Manual

Processor 7/7

CFG Straps for Processor
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2 1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed
CFG2 R40 *1K_04
Display Port Presence Strap
1:(Default) Disabled; No Physical Display Port
CFG4
attached to Embedded Display Port
0:Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG4 R31 *1K_04
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
CFG[6:5]
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG5 R41 *1K_04
CFG6 R45 *1K_04
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB de assertion
CFG7
0: PEG Wait for BIOS for training
CFG7
R46 *1K_04
R380
3.3V
Sandy Bridge Processor 7/7
( RESERVED )
U23E
AK28
CFG0
CFG[0]
AK29
CFG[1]
CFG2 AL26
CFG[2]
AL27
AK26 CFG[3]
CFG4
CFG[4]
CFG5 AL29
CFG[5]
CFG6 AL30
AM31 CFG[6]
CFG7
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
AM26 CFG[10]
CFG[11]
AN28
CFG[12]
AN31
AN26 CFG[13]
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
H_CPU_RSVD1
VAXG_VAL_SENSE
H_CPU_RSVD2 AH31
VSSAXG_VAL_SENSE
H_CPU_RSVD3 AJ33
AH33 VCC_VAL_SENSE
H_CPU_RSVD4
VSS_VAL_SENSE
AJ26
RSVD5
B4
VREF_CH_A_DIMM
D1 RSVD6
VREF_CH_B_DIMM
RSVD7
F25
RSVD8
F24
RSVD9
F23
D24 RSVD10
RSVD11
G25
RSVD12
G24
E23 RSVD13
D23 RSVD14
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
A30 RSVD21
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
A19
VCCIO_SEL
J15
RSVD27
47989-0732
10K_04
R381 *10mil_04 H_SNB_IVB#_PWRCTRL
On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
2,3,11,14,15,18,23,24,26,28,29,30,32,33,36,37,39,40
L7
RSVD28
AG7
RSVD29 AE7
RSVD30
AK2
RSVD31
W8
RSVD32
AT26
RSVD33
AM33
RSVD34 AJ27
RSVD35
T8
RSVD37 J16
RSVD38
H16
RSVD39
G16
RSVD40
AR35
RSVD41 AT34
RSVD42
AT33
RSVD43
AP35
RSVD44 AR34
RSVD45
B34
RSVD46 A33
RSVD47 A34
RSVD48
B35
RSVD49
C35
RSVD50
1.5V
R213 *0_04
AJ32
RSVD51
AK32
R210
RSVD52
Q12 1K_1%_04
*AO3402L
AH27 VREF_CH_A_DIMM S D
VCC_DIE_SENSE
R214 R212
AN35
*1K_04
RSVD54
AM35 1K_1%_04
RSVD55
DRAMRST_CNTRL
DRAMRST_CNTRL 3,15
AT2
RSVD56
AT1
RSVD57 AR1 1.5V
RSVD58
R206 *0_04
B1
R203
KEY
Q11
*AO3402L 1K_1%_04
S D
VREF_CH_B_DIMM
R209 R202
*1K_04
1K_1%_04
DRAMRST_CNTRL
3,6,9,10,21,26,28,29,36,37 1.5V
3.3V
Schematic Diagrams
Sheet 8 of 48
Processor 7/7
MVREF_DQ_DIMMA 9
MVREF_DQ_DIMMB 10
Processor 7/7 B - 9