Processor 2/7 - Clevo W130HU Service Manual

Schematic Diagrams

Processor 2/7

PU/PD for JTAG signals
1.05VS_VTT
Sheet 3 of 48
Processor 2/7
B - 4 Processor 2/7
Sandy Bridge Processor 2/7
R322 51_04 XDP_TMS
R320 51_04 XDP_TDI_R
R321 *51_04 XDP_PREQ#
XDP_TDO_R
R323 51_04
XDP_TCLK
R324 51_04
R319 51_04 XDP_TRST#
H_SNB_IVB#
19 H_SNB_IVB#
3.3VS
R338 1K_04 XDP_DBR_R
H_CATERR#
R334 *10mil_04 H_PECI_R
19,27 H_PECI
R47 56_1%_04 H_PROCHOT#_D
41 H_PROCHOT#
If PROCHOT# is not used, then it must
be terminated with a 68-O +-5% pull-up
resistor to 1.05VS_VTT .
R331 *10mil_04 H_THRMTRIP#_R
19 H_THRMTRIP#
R335 *10mil_04 PM_SY NC_R
16 H_PM_SY NC
H_CPUPWRGD_R
R333 *10mil_04
19 H_CPUPWRGD
PMSY S_PWRGD_BUF R327 130_1%_04 VDDPWRGOOD_R
Buffered reset to CPU
1.05VS_VTT BUF_CPU_RST#
R318 75_1%_04 R317 43.2_1%_04
6-13-43R21-28C
6
3.3VS
D
Q25A
R313 10K_04 2 G MTDN7002ZHS6R
S
3 1
D
5 G Q25B
S MTDN7002ZHS6R
4
R325 *1.5K_1%_04
18,25 PLT_RST#
27
R330
R315 C286
*750_1%_04
100K_04 68p_50V_NPO_04
CAD Note: Capacitor
need to be placed
close to buffer output pin
( CLK,MISC,JTAG )
U23B
A28
BCLK
C26 A27
PROC_SELECT# BCLK#
AN34
SKTOCC#
A16
DPLL_REF_SSCLK
A15
DPLL_REF_SSCLK#
AL33
CATERR#
AN33 R8 CPUDRAMRST#
PECI SM_DRAMRST#
AL32 AK1
SM_RCOMP_0
PROCHOT# SM_RCOMP[0]
A5 SM_RCOMP_1
SM_RCOMP[1]
A4 SM_RCOMP_2
SM_RCOMP[2]
AN32
THERMTRIP#
AP29
XDP_PRDY #
PRDY #
AP27
XDP_PREQ#
PREQ#
AR26 XDP_TCLK
TCK
AR27 XDP_TMS
TMS
AM34 AP30 XDP_TRST#
PM_SYNC TRST#
AR28
XDP_TDI_R
TDI
AP26 XDP_TDO_R
TDO
AP33
UNCOREPWRGOOD
AL35
XDP_DBR_R
DBR#
V8
SM_DRAMPWROK
AT28 XDP_BPM0_R
BPM#[0] AR29
XDP_BPM1_R
BPM#[1] AR30
XDP_BPM2_R
BPM#[2]
AR33 AT30 XDP_BPM3_R
RESET# BPM#[3]
AP32 XDP_BPM4_R
BPM#[4]
AR31 XDP_BPM5_R
BPM#[5]
AT31 XDP_BPM6_R
BPM#[6] AR32
XDP_BPM7_R
BPM#[7]
47989-0732
H_PROCHOT#
Q6
G
H_PROCHOT_EC
MTN7002ZHS3 C76
47p_50V_NPO_04
10/1 R39 100K_04
R36 *0_04
2,8,11,14,15,18,23,24,26,28,29,30,32,33,36,37,39,40
9,10,11,12,13,14,16,17,18,19,20,21,23,25,27,28,29,30,33,36,41
Processor Pullups/Pull downs
H_PROCHOT# R35 62_04
H_CPUPWRGD_R
R332 10K_04
C289 *0.1u_10V_X7R_04
TRACE WIDTH 10MIL, LENGTH <500MILS
DDR3 Compensation Signals
CLK_EXP_P 15
CLK_EXP_N 15
SM_RCOMP_0 R339 140_1%_04
CLK_DP_P 15
SM_RCOMP_1
R379 25.5_1%_04
CLK_DP_N 15
SM_RCOMP_2 R375 200_1%_04
S3 circuit:- DRAM PWR GOOD logic
3.3V 1.5VS_CPU
R310
*200_1%_04
D20
1
A
16 PM_DRAM_PWRGD
3
C
2 A
16,37 1.8VS_PWRGD
*BAT54AWGH
R316 0_04
G
36,37,39 SUSB
S3 circuit:- DRAM_RST# to memory
should be high during S3
1.5V
R204 *0_04 R208
1K_04
Q10
MTN7002ZHS3
CPUDRAMRST# S D R207 1K_04
R200
DRAMRST_CNTRL 8,15
C231
0.047u_10V_X7R_04
2,5,19,20,21,39,41 1.05VS_VTT
6,36 1.5VS_CPU
6,8,9,10,21,26,28,29,36,37 1.5V
3.3V
3.3VS
1.05VS_VTT
R328
10K_04
PMSY S_PWRGD_BUF
R314
*39_04
Q24
*MTN7002ZHS3
DDR3_DRAMRST# 9,10