IMS 5000 Series Manual page 69

CONFIGURING THE 861 BOARD
I/O Address Selection (Location IE)
The most significant bits of the I/O addresses used by the 861 board are assigned values
according to the shunts at location JE.
If a shunt is on, the corresponding address bit
has a '0' value;
if
a shunt is off, the bit has a 'I' value.
JE
A7 1
0 0
12
A6 2
0 0
11
AS 3
0 0
10
A4 4
0
0
9
A3 5
0 0
8
A2 6
0
0
7
Each 861 board is assigned
a
unique address according to the table bdow:
1st
2nd
3rd
4th
5th
6th
7th
8th
I/O Address
J::!u
Binary
40H 010000XX
44H 010001XX
48H 010010XX
4CH 010011XX
50H 010100XX
54H 010101XX
58H 010 110XX
5CH 010 ll1XX
9th
10th
11th
12th
13th
14th
15th
16th
I/O Address
.l::iu.
Binar y
EO H 111000XX
E4H 111001XX
E8H 111010XX
ECH 111011XX
FOH 111100XX
F4H 111101XX
F8H 111110XX
FCH 111111XX
Interrupt Level Selection (Location JF)
The interrupt levd for the 861 board can be sdected by
a
shunt on JF.
JF
V 10 1
0
V II 2
0
V I 2 3
0
V 13 4
0
V I 4 5
0
V I 5 6
0
VI6 7
0
VI7 8
0
o 16
o
15
o
14
o
13
o 12
o 11
o 10
o 9
IMS International
5000 Series Microcorrputer s/7.0 1.8 3;P age 67