IMS 5000 Series Manual page 24

I/O DEVICE ADDRESSES FOR THE 971 CPU BOARD
18H
bit 0
1BH
bit 0
20H-27H
20H
20H
21H
21H
22H
23H
24H
25H
26H
27H
28H-2FH
28H
28H
29H
29H
2AH
2BH
2CH
2DH
2EH
2FH
60H-7FH
60H
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
6EH
6FH
70H
7lH
72H
73H
74H
75H
76H
7FH
2716/32/64 EPROM Enable
EPROM is disabled when bit 0=1.
58167 CLK Interrupt Mask
58167 CLK Interrupt is enabled when bit O=l.
Port 0 8250 ACE Internal Register Select
Read Receive buffer/ Write Holding Register (DLAB=O)
Write Divisor Latch least significant byte (DLAB=1)
R/W Interrupt Enable Register
(D
LAB=O)
Write Divisor Latch most significant byte
Read Interrupt Identification Register
R/W Line Control Register
R;W Modem Control Register
R/W Line Status Register
R;W Modem Status Register
Nothing
Port 1 8250 ACE Internal Register Select
Read Receive buffer/ Write Holding Register (DLAB=O)
Write Divisor Latch least significant byte (DLAB=1)
R/W Interrupt Enable Register (DLAB=O)
Write Divisor Latch most significant byte
Read Interrupt Identification Register
R/W Line Control Register
R;W Modem Control Register
R/W Line Status Register
R;W Modem Status Register
Nothing
58167 Clock Internal Register Select
R;W Counter - Thousandths of Seconds
R/W Counter - Hundredths and Tenths of Seconds
R;W Counter - Seconds
R/W Counter - Minutes
R;W Counter - Hours
R/W Counter - Day of the Week
R;W Counter - Day of the Month
R/W Counter - Month
R/W Latches - Thousandths of Seconds
R/W Latches - Hundredths and Tenths of Seconds
R/W Latches - Seconds
RjW Latches - Minutes
RjW Latches - Hours
RjW Latches - Day of the Week
RjW Latches - Day of the Month
RjW Latches - Month
R/O Interrupt Status Register
W/O Interrupt Control Register
W/O Counter Reset
W/O Latch Reset
R/O Status Bit
W/O "GO" Command
W/O Standby Interrupt
Test Mode
'-./
J
IMS International
5000 Series Microcomputers/7.0 l.83/page 22