IMS 5000 Series Manual page 27

I/O DEVICE ADDRESSES FOR THE 881 CPU BOARD
06H-7FH
60H-7FH
60H
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
6EH
6FH
70H
71H
72H
73H
74H
75H
76H
7FH
8259 Command and Status Select
58167 Clock Internal Register Select
R/W Counter - Thousandths of seconds
R/W Counter - Hundredths and tenths of seconds
R/W Counter - Seconds
R/W Counter - Minutes
R/W Counter - Hours
R/W Counter - Day of the week
R/W Counter - Day of the month
R/W Counter - Months
R/W Latches - Thousandths of seconds
R/W Latches - Hundredths and tenths of secortds
R/W Latches - Seconds
R/W Latches - M1nutes
R/W Latches - Hours
R/W Latches - 0 ay of the week
R/W Latches - 0 ay of the month
R/W Latches - Months
RIO Interrupt Status Register
WIO Interrupt Control Register
WIO Counter Reset
WIO Latch Reset
RIO Status Bit
WIO "GO" Command
WIO Standby Interrupt
Test Mode
,-,I
CONFIGURING THE 881 BOARD
EPROM Type Selection <IAl
If a 2716 (2K) EPROM is used in location 5B, then the upper pair of pins at
location JA should be shunted.
If
the EPROM is a 2732 (4K) or a 2764 (8K),
the lower pair should be shunted.
Numeric Processor Interrupt Enable <IB)
If the board has an 8087 in location 3B, location JB should be unshunted. If
there is no 8087, JB should be shunted to mask out the numeric processor
interrupt. Normally, J B is etched.
MWRT+ Enable <IC)
If this location is shunted, the MWRT+ signal (Memory Write) 1S sent out to the
S-100 bus. Normally, it is unshunted.
IMS International
5000 Series Microcomputersj7.01.83;Page 25