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Parity Error Interrupt Level (Jack IG)
Jack JG allows selection of eight different responses to a parity error.
The
sdections are:
Shunt
Position
VIl
VIz
VB
VI4
VI5
INT
NMI
ROY
Interrupt
Selected
VECTORED INTERRUPT 1
VECTORED INTERRUPT 2
VECTORED INTERRUPT 3
VECTORED INTERR UPT 4
VECTORED INTERRlJ'PT 5
INT Line
Non-maskable INT
(2-
BO Only)
PRDY Line
(Parity Error Stops CPU)
The state of the parity circuit may be sensed by reading the I/O port on the
memory board.
If
bit 0 is a "1", a parity error has occurred.
Normally, VI2 is shunted for CP/M systems; there are no shunts for TurboDOS.
Normal/Bank Mode (Jack IE)
This shunt should be installed only if the board is to be used in the Bank
S wi tched mode.
In the normal mode (unshunted) the board will respond to all
addresses from 0000 to FFFF hex.
In the normal mode, with shunt JE removed, the four 16K memory banks occupy
the entire 16 bit address space 0000 through FFFF hex.
In this mode, each 16K
bank may be controlled individually by an output to the board's I/O port.
A
"one" bit disables the associated bank.
Control is on a bit basts, thus:
Output
BIT 0=1
BIT 1=1
BIT 2= 1
BIT 3=1
Controlled Memory Bank (hex)
J
0000-3FFF
4000-7FFF
BOOO-BFFF (omitted in 32K vers.)
COOO-FFFF (omitted in 32K
&
4BK vers.)
In the Bank Mode (Shunt JE installed) the board responds to a combination of
bits.
Codes are provided for a variety of configurations defined in the following
table.
Initially, the board is deselected by the Power On Clear signal.
The 465
memory board can be used in a 16K, 32K or 48K bank sdection scheme.
IMS International
5000 Series Microcomputer 5/7.01.8 3/pag e 28
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