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MVME1600-001 Base Board Preparation
1
General-Purpose Software-Readable Header (J8)
1-8
Header J8 provides eight readable jumpers. These jumpers can be
read as a register at ISA I/O address $80000801. Bit 0 is associated
with header pins 1 and 2; bit 7 is associated with pins 15 and 16. The
bit values are read as a zero when the jumper is installed, and as a
one when the jumper is removed. The PowerPC firmware
(PPCBug) reserves the four lower-order bits, SRH3 to SRH0. They
are defined as shown in the list below:
Low-Order Bit
Pins
Bit #0 (SRH0)
1—2
Bit #1 (SRH1)
3—4
Bit #2 (SRH2)
5—6
Bit #3 (SRH3)
7—8
The four higher-order bits, SRH4 to SRH7, are user-definable. They
can be allocated as necessary to specific applications. The
MVME1600-001 is shipped from the factory with J8 set to all zeros
(jumpers on all pins).
J8
PPCBug INSTALLED
SRH7
16
15
USER-DEFINABLE
SRH6
USER-DEFINABLE
SRH5
USER-DEFINABLE
SRH4
USER-DEFINABLE
SRH3
8
7
RESERVED FOR FUTURE USE
SRH2
RESERVED FOR FUTURE USE
SRH1
SETUP PARAMETER SOURCE (IN=NVRAM; OUT=ROM)
SRH0
2
1
RESERVED FOR FUTURE USE
Definition
Reserved for future use.
With the jumper installed between pins 3 and 4
(factory configuration), the debugger uses the
current user setup/operation parameters in
NVRAM. When the jumper is removed
(making the bit a 1), the debugger uses the
default setup/operation parameters in ROM
instead. Refer to the ENV command
description in Chapter 6 for the ROM defaults.
Reserved for future use.
Reserved for future use.
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