NXP Semiconductors ColdFire MCF52230 Manuals

Manuals and User Guides for NXP Semiconductors ColdFire MCF52230. We have 1 NXP Semiconductors ColdFire MCF52230 manual available for free PDF download: Reference Manual

NXP Semiconductors ColdFire MCF52230 Reference Manual (658 pages)

Integrated

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 10 MB

Table of Contents
3
Chapter 1 Overview

12
- MCF52235 Family Configurations
  12
- Block Diagram
  12
- Part Numbers and Packaging
  14
- Features
  14
Chapter 2 Signal Descriptions

25
- Introduction
  25
- Overview
  25
- Reset Signals
  32
- PLL and Clock Signals
  32
- Mode Selection
  32
- External Interrupt Signals
  32
- Queued Serial Peripheral Interface (QSPI)
  33
- Fast Ethernet Controller PHY Signals
  34
- I 2 C I/O Signals
  34
- UART Module Signals
  35
- 2.11 DMA Timer Signals
  35
- 2.12 ADC Signals
  35
- 2.13 General Purpose Timer Signals
  36
- 2.14 Pulse Width Modulator Signals
  36
- 2.15 Debug Support Signals
  36
- 2.16 Ezport Signal Descriptions
  37
- 2.17 Power and Ground Pins
  38
Chapter 3 Coldfire Core

41
Chapter 4 Enhanced Multiply-Accumulate Unit (EMAC)

67
- Multiply-Accumulate Unit
  67
- Introduction to the MAC
  68
- General Operation
  68
- Memory Map/Register Definition
  71
- EMAC Instruction Set Summary
  77
- CAU Registers
  85
- CAU Operation
  86
- CAU Commands
  86
- CAU Equate Values
  91
Chapter 5 Random Number Generator Accelerator (RNGA)

93
- Overview
  93
- Features
  94
- Modes of Operation
  94
- Memory Map/Register Definition
  95
- Functional Description
  103
- Initialization/Application Information
  104
Chapter 7 Clock Module

107
- Introduction
  107
- Features
  107
- Modes of Operation
  107
- Low-Power Mode Operation
  108
- Block Diagram
  108
- Signal Descriptions
  110
- Memory Map and Registers
  111
- Functional Description
  117
Chapter 8 Real Time Clock

127
- Introduction
  127
- Memory Map/Register Definition
  128
- Functional Description
  138
- Initialization/Application Information
  139
Chapter 9 Power Management

150
- Functional Description
  151
Chapter 10 Reset Controller Module

161
- Introduction
  161
- Block Diagram
  161
- Signals
  162
- Memory Map and Registers
  162
- Functional Description
  165
Chapter 11 Static RAM (SRAM)

171
- Introduction
  171
- Memory Map/Register Description
  171
- Initialization/Application Information
  173
Chapter 12 Chip Configuration Module (CCM)

175
- Introduction
  175
- External Signal Descriptions
  176
- Memory Map/Register Definition
  177
- Functional Description
  179
- Reset
  180
Chapter 13 System Control Module (SCM)

181
- Introduction
  181
- Overview
  181
- Features
  181
- Memory Map and Register Definition
  182
- Register Descriptions
  183
- Internal Bus Arbitration
  191
- System Access Control Unit (SACU)
  194
- Overview
  194
- Features
  195
- Memory Map/Register Definition
  195
- Register Descriptions
  206
- Ports Interrupts
  215
Chapter 14 Interrupt Controller Module

217
- Coldfire Interrupt Architecture Overview
  217
- Memory Map
  220
- Register Descriptions
  221
- Low-Power Wakeup Operation
  234
Chapter 16 Edge Port Module (EPORT)

237
- Introduction
  237
- Low-Power Mode Operation
  238
- Interrupt/Gpio Pin Descriptions
  238
- Memory Map/Register Definition
  239
Chapter 17 Coldfire Flash Module (CFM)

243
- Introduction
  243
- External Signal Description
  245
- Memory Map and Register Definition
  245
- Functional Description
  256
Chapter 18 Fast Ethernet Controller (FEC)

273
- Overview
  273
- Modes of Operation
  273
- FEC Top-Level Functional Diagram
  275
- Functional Description
  276
- Programming Model
  289
- Buffer Descriptors
  314
Chapter 19 Ethernet Physical Transceiver (EPHY) Block Description

321
- Introduction
  321
- External Signal Descriptions
  323
- Memory Map and Register Descriptions
  325
- Functional Description
  341
Chapter 20 DMA Controller Module

353
- Introduction
  353
- M-Bus Priority Level (MPL)
  356
- DMA Transfer Overview
  356
- Memory Map/Register Definition
  357
- Functional Description
  368
Chapter 21 Ezport

373
- Features
  373
- Modes of Operation
  373
- External Signal Description
  374
- Command Definition
  375
- Functional Description
  379
- Initialization/Application Information
  380
Programmable Interrupt Timer Modules (PIT0-PIT1)

381
- Introduction
  381
- Memory Map/Register Definition
  382
- Functional Description
  385
Chapter 22 General Purpose Timer Module (GPT)

387
- Introduction
  387
- Block Diagram
  388
- Low-Power Mode Operation
  389
- Signal Description
  389
- Memory Map and Registers
  390
- Functional Description
  403
- Reset
  407
- Interrupts
  407
Chapter 24 DMA Timers (DTIM0-DTIM3)

409
- Introduction
  409
- Memory Map/Register Definition
  410
- Functional Description
  416
- Initialization/Application Information
  416
Chapter 25 Queued Serial Peripheral Interface (QSPI)

419
- Introduction
  419
Chapter 26

435
- Introduction
  435
- Memory Map/Register Definition
  438
- I 2 C Programming Examples
  480
Chapter 27 Analog-To-Digital Converter (ADC)

485
- Introduction
  485
- Features
  485
- Block Diagram
  485
- Functional Description
  486
- Register Definitions
  502
Chapter 29 Pulse Width Modulation (PWM) Module

529
- Introduction
  529
- Memory Map/Register Definition
  530
- Functional Description
  540
Chapter 30

551
- Introduction
  551
- External Signal Description
  555
- Memory Map/Register Definition
  555
- Functional Overview
  570
- Flexcan Initialization Sequence
  578
Chapter 31 Debug Module

581
- Introduction
  581
- External Signal Description
  582
- Real-Time Trace Support
  583
- Memory Map/Register Definition
  586
- Background Debug Mode (BDM)
  597
- Real-Time Debug Support
  617
- Processor Status, DDATA Definition
  620
- Freescale-Recommended BDM Pinout
  624
Chapter 32 IEEE 1149.1 Test Access Port (JTAG)

627
- Introduction
  627
- External Signal Description
  628
- Memory Map/Register Definition
  630
- Functional Description
  632
- Initialization/Application Information
  636
Appendix A Register Memory Map Quick Reference

637

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NXP Semiconductors ColdFire MCF52230 Manuals

NXP Semiconductors ColdFire MCF52230 Reference Manual (658 pages)

Table of Contents

Chapter 1 Overview

Chapter 2 Signal Descriptions

Chapter 3 Coldfire Core

Chapter 4 Enhanced Multiply-Accumulate Unit (EMAC)

Chapter 5 Random Number Generator Accelerator (RNGA)

Chapter 7 Clock Module

Chapter 8 Real Time Clock

Chapter 9 Power Management

Chapter 10 Reset Controller Module

Chapter 11 Static RAM (SRAM)

Chapter 12 Chip Configuration Module (CCM)

Chapter 13 System Control Module (SCM)

Chapter 14 Interrupt Controller Module

Chapter 16 Edge Port Module (EPORT)

Chapter 17 Coldfire Flash Module (CFM)

Chapter 18 Fast Ethernet Controller (FEC)

Chapter 19 Ethernet Physical Transceiver (EPHY) Block Description

Chapter 20 DMA Controller Module

Chapter 21 Ezport

Programmable Interrupt Timer Modules (PIT0-PIT1)

Chapter 22 General Purpose Timer Module (GPT)

Chapter 24 DMA Timers (DTIM0-DTIM3)

Chapter 25 Queued Serial Peripheral Interface (QSPI)

Chapter 26

Chapter 27 Analog-To-Digital Converter (ADC)

Chapter 29 Pulse Width Modulation (PWM) Module

Chapter 30

Chapter 31 Debug Module

Chapter 32 IEEE 1149.1 Test Access Port (JTAG)

Appendix A Register Memory Map Quick Reference

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