Silicon Laboratories Si5316 Series Reference Manual page 91

HIST_DEL[4:0]
01000
01001
01010
01011
01100
01101
01110
01111
HIST_AVG[4:0] History Averaging Time (ms)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
If a highly stable reference, such as an oven-controlled crystal oscillator (OCXO) is supplied at XA/XB, an
extremely stable digital hold can be achieved. If a crystal is supplied at the XA/XB port, the digital hold stability will
be limited by the stability of the crystal. Table 6, "AC Characteristics—All Parts" gives the specifications related to
the digital hold function.
7.6.2. Recovery from Digital Hold (Si5319, Si5326, Si5368)
When the input clock signal returns, the device transitions from digital hold to the selected input clock. The device
performs hitless recovery from digital hold. The clock transition from digital hold to the returned input clock includes
"phase buildout" to absorb the phase difference between the digital hold clock phase and the input clock phase.
Table 47. Digital Hold History Delay (Continued)
History Delay Time (ms)
0.03
0.05
0.10
0.20
0.41
0.82
1.64
3.28
Table 48. Digital Hold History Averaging Time
0.0000
0.0004
0.001
0.003
0.006
0.012
0.03
0.05
0.10
0.20
0.41
0.82
1.64
3.28
6.55
13
HIST_DEL[4:0]
11000
11001
11010
11011
11100
11101
11110
11111
HIST_AVG[4:0]
10000
10001
10010
10011
10100
10101
10110
10111
11000 (default)
11001
11010
11011
11100
11101
11110
11111
Rev. 0.41
Si53xx-RM
History Delay Time (ms)
1678
3355
6711
13422
26844
53687
107374
214748
History Averaging Time (ms)
26
52
105
210
419
839
1678
3355
6711
13422
26844
53687
107374
214748
429497
858993
91