Si5365 - Silicon Laboratories Si5316 Series Reference Manual

3.7. Si5365

The Si5365 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC-
48/OC-192, Ethernet, and Fibre Channel, in which the application requires clock multiplication without jitter
attenuation. The Si5365 accepts four clock inputs ranging from 19.44 MHz to 707 MHz and generates five
frequency-multiplied clock outputs ranging from 19.44 MHz to 1050 MHz. The input clock frequency and clock
multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel, broadcast video rates.
The DSPLL loop bandwidth is digitally selectable, providing jitter performance optimization at the application level.
Operating from a single 1.8 or 2.5 V supply, the Si5365 is ideal for providing clock multiplication in high
performance timing applications. See "6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)" on page 48
for a complete description.
CKIN_1+ 2
÷ N3_1
CKIN_1–
CKIN_2+
2
÷ N3_2
CKIN_2–
2
CKIN_3+
÷ N3_3
CKIN_3–
2
CKIN_4+
÷ N3_4
CKIN_4–
C1B
C2B
C3B
ALRMOUT
C1A
C2A
Control
CS0_C3A
CS1_C4A
f
3
®
DSPLL
Bandwidth
Control
Figure 7. Si5365 Clock Multiplier Block Diagram
Rev. 0.41
÷ NC1
f
OSC
÷ N1_HS ÷ NC2
÷ NC3
÷ N2
÷ NC4
÷ NC5
Si53xx-RM
BYPASS/DSBL2
1
CKOUT_1+
2
CKOUT_1–
0
1
2 CKOUT_2+
CKOUT_2–
0
DBL2_BY
1
CKOUT_3+
2
CKOUT_3–
0
DBL34
DIV34[1:0]
1
CKOUT_4+
2
CKOUT_4–
0
1
2 CKOUT_5+
CKOUT_5–
0
DBL5
VDD (1.8 V or 2.5 V)
GND
21