Silicon Laboratories Si5316 Series Reference Manual page 90

Si53xx-RM
7.6. Digital Hold
All Any-Rate Precision Clock devices feature a holdover mode, whereby the DSPLL is locked to a digital value.
7.6.1. Narrowband Digital Hold (Si5316, Si5326, Si5368)
After the part's initial self-calibration (ICAL), when no valid input clock is available, the device enters digital hold.
Referring to the logical diagram in "Appendix D—Alarm Structure" on page 139, lack of clock availability is defined
by following boolean equation for the Si5326 and Si5325:
NOT(LOS1_INT OR FOS1_INT) AND (LOS2_INT OR FOS2_INT) = enter digital hold
The equivalent boolean equation for the Si5367 and Si5368 is as follows:
NOT(LOS1_INT OR FOS1_INT) AND (LOS2_INT OR FOS2_INT) AND
(LOS3_INT OR FOS3_INT) AND (LOS4_INT OR FOS4_INT) = enter digital hold
7.6.1.1. Digital Hold Detailed Description (Si5326, Si5368)
In this mode, the device provides a stable output frequency until the input clock returns and is validated. Upon
entering digital hold, the internal DCO is initially held to its last frequency value, M (See Figure 26). Next, the DCO
slowly transitions to a historical average frequency value supplied to the DSPLL, M
Values of M starting from time t = –(HIST_DEL + HIST_AVG) and ending at t = –HIST_DEL are averaged to
compute M . This historical average frequency value is taken from an internal memory location that keeps a
HIST
record of previous M values supplied to the DCO. By using a historical average frequency, input clock phase and
frequency transients that may occur immediately preceding digital hold do not affect the digital hold frequency.
Also, noise related to input clock jitter or internal PLL jitter is minimized.
The history delay can be set via the HIST_DEL[4:0] register bits as shown in Table 47 and the history averaging
time can be set via the HIST_AVG[4:0] register bits as shown in Table 48. The DIGHOLDVALID register can be
used to determine if the information in HIST_AVG is valid and the device can enter SONET/SDH compliant digital
hold. If DIGHOLDVALID is not active, the part will enter VCO freeze instead of digital hold.
HIST_DEL[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
90
t = –HIST_DEL
HIST_AVG
M
HIST
Figure 26. Parameters in History Value of M
Table 47. Digital Hold History Delay
History Delay Time (ms)
0.0001
0.0002
0.0004
0.0008
0.0016
0.0032
0.0064
0.01
Digital Hold
@
t = 0
Time
M
HIST_DEL[4:0]
10000
10001
10010 (default)
10011
10100
10101
10110
10111
Rev. 0.41
, as shown in Figure 26.
HIST
History Delay Time (ms)
6.55
13
26
52
105
210
419
839