Silicon Laboratories Si5316 Series Reference Manual page 99

7.11. Alarms (Si5319, Si5325, Si5326, Si5367, Si5368)
Summary alarms are available to indicate the overall status of the input signals and frame alignment (Si5368 only).
Alarm outputs stay high until all the alarm conditions for that alarm output are cleared. The Register VALTIME
controls how long a valid signal is re-applied before an alarm clears. Table 53 shows the available settings. Note
that only for VALTIME[1:0] = 00, hitless switching is not possible.
7.11.1. Loss-of-Signal Alarms (Si5319, Si5325, Si5326, Si5367, Si5368)
The device has loss-of-signal circuitry that continuously monitors CKINn for missing pulses. The LOS circuitry
generates an internal LOSn_INT output signal that is processed with other alarms to generate CnB and
ALARMOUT.
An LOS condition on CKIN1 causes the internal LOS1_INT alarm become active. Similarly, an LOS condition on
CKINn causes the LOSn_INT alarm become active. Once a LOSn_INT alarm is asserted on one of the input
clocks, it remains asserted until that input clock is validated over a designated time period. The time to clear
LOSn_INT after a valid input clock appears is listed in Table 6, "AC Characteristics—All Parts". If another error
condition on the same input clock is detected during the validation time then the alarm remains asserted and the
validation time starts over.
7.11.1.1. Narrowband LOS Algorithms (Si5319, Si5326, Si5368)
There are three options for LOS: LOS, LOS_A, and no LOS, which are selected using the LOSn_EN registers.
The values for the LOSn_EN registers are given in Table 54.
7.11.1.2. Standard LOS (Si5319, Si5326, Si5368)
To facilitate automatic hitless switching, the LOS trigger time can be significantly reduced while in narrowband
mode by using the default LOS option (LOSn_EN = 11). The LOS circuitry divides down each input clock to
produce a 2 kHz to 2 MHz signal. The LOS circuitry over samples this divided down input clock using a 40 MHz
clock to search for extended periods of time without input clock transitions. If the LOS monitor detects twice the
normal number of samples without a clock edge, an LOS alarm is declared. Table 6, "AC Characteristics—All
Parts" gives the minimum and maximum amount of time for the LOS monitor to trigger. The LOSn trigger window is
based on the value of the input divider N3. The value of N3 is reported by DSPLLsim.
The range over which LOS is guaranteed to not produce false positive assertions is 100 ppm. For example, if a
device is locked to an input clock on CKIN1, the frequency of CKIN2 should differ by no more than 100 ppm to
avoid false LOS2 assertions.
Table 53. Loss-of-Signal Validation Times
VALTIME[1:0] Clock Validation Time
00
(hitless switching not available)
01
10
11
Table 54. Loss-of-Signal Registers
LOSn_EN[1:0]
00 Disable all LOS monitoring
01
10
11
Rev. 0.41
2 ms
100 ms
200 ms
13 s
LOS Selection
Reserved
LOS_A enabled
LOS enabled
Si53xx-RM
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