Si5319 - Silicon Laboratories Si5316 Series Reference Manual

Si53xx-RM

3.2. Si5319

The Si5319 is a jitter-attenuating precision M/N clock multiplier for applications requiring sub 1 ps jitter
performance. The Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output
ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5319 can also use its crystal oscillator as
a clock source for frequency synthesis. The device provides virtually any frequency translation combination across
this operating range. The Si5319 input clock frequency and clock multiplication ratio are programmable through an
I2C or SPI interface. The Si5319 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which
provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the
need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable,
providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply,
the Si5319 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications.
See "7. Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367, Si5368)" on page 74 for a complete
description.
XO
÷ N32
÷ N31
CKIN
Loss of Signal
Loss of Lock
16
Xtal or Refclock
DSPLL
f
3
Signal Detect
2
I C/SPI Port
Device Interrupt
Rate Select
Figure 2. Si5319 Clock Multiplier Block Diagram
Rev. 0.41
®
÷ N1_HS ÷ NC1
÷ N2
Control
Xtal/Clock Select
CKOUT
VDD (1.8, 2.5, or 3.3 V)
GND