HP E3473A User Manual page 101

Specifications and Characteristics
Electrical Specifications
Characteristic
RES rise time
RES fall time
RESET pulse width
MRESET pulse width
NMI rise time
NMI fall time
RES setup time
MRES setup time
NMI setup time
IRQ0 - IRQ7 setup time
(edge detection time)
IRQ0 - IRQ7 setup time
(level detection time)
NMI hold time
IRQ0 - IRQ7 hold time
IRQOUT output delay time
Bus request setup time
Bus acknowledge delay time 1
Bus acknowledge delay time 2
Bus 3-state delay time
*1 Typical outputs measured with 50pF load
86
Table 8-10. Clock Signal Timing (E3473A)
Symbol SH7050
min max
t - 200
RESr
t - 200
RESf
t 20 -
RESW
t TBD -
MRESW
t - 200
NMIr
t - 200
NMIf
t 30 -
RESS
t TBD -
MRESS
t 30 -
NMIS
t 30 -
IRQES
t 30 -
IRQLS
t TBD -
NMIH
t TBD -
IRQEH
t - 25
IRQOD
t TBD -
BRQS
t - TBD
BACD1
t - TBD
BACD2
t - TBD
BZD
(*1)
Typical Worst Case
min max min
-
-
20
TBD
-
-
80
TBD+10
90
40
40
TBD
TBD
-
TBD+10
-
-
-
Unit
max
200 ns
200 ns
- t
cyc
- t
cyc
200 ns
200 ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
30 ns
- ns
TBD+5 ns
TBD+5 ns
TBD+5 ns