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APPLICATIO S I FOR ATIO
50A I
RATING
PK
12V
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
Figure 9. Plugging into the Cigarette Lighter
Design Example
As a design example, assume V
22V(max), V
= 1.6V(nominal), 1.8V to 1.3V range, I
OUT
= 12A and f = 275kHz. R
SENSE
be calculated:
R
= 50mV/12A = 0.0042Ω
SENSE
7
C
= 1.61(10
)/(275kHz) – 11pF = 47pF
OSC
Assume a 1.2µH inductor and check the actual value of the
ripple current. The following equation is used :
V
V
∆I
=
OUT
OUT
– 1
L
( )( )
f L
V
IN
The highest value of the ripple current occurs at the
maximum input and output voltages:
1 8
.
V
∆I
=
L
µ
275
kHz
( .
1 2
H
)
The maximum ripple current is 42% of maximum output
current, which is about right.
Next, verify the minimum on-time of 200ns is not violated.
The minimum on-time occurs at maximum V
mum V
.
OUT
V
OUT
=
( )
t
ON MIN
(
)
V
f
IN MAX
(
)
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Fairchild FDS6612A results
V
IN
LTC1736
1736 F09
= 12V(nominal), V
IN
and C
can immediately
OSC
1 8
.
V
=
1
–
5
A
22
V
and mini-
IN
1 3
.
V
=
=
215
ns
22 275
V
(
kHz
)
in: R
= 0.03Ω, C
DS(ON)
voltage with T(estimated) = 50°C:
( )
1 6
.
V
=
P
MAIN
22
V
( ) ( )( ) (
+
1 7 22
.
=
571
mW
Because the duty cycle of the bottom MOSFET is much
greater than the top, two larger MOSFETs must be paral-
leled. Choosing Fairchild FDS6680A MOSFETs yields a
=
IN
parallel R
of 0.0065Ω. The total power dissipaton
DS(ON)
MAX
for both bottom MOSFETs, again assuming T = 50°C, is:
22
V
– .
=
P
SYNC
22
=
955
mW
Thanks to current foldback, the bottom MOSFET dissipaton
in short circuit will be less than under full-load conditions.
C
is chosen for an RMS current rating of at least 6A at
IN
temperature. C
OUT
output ripple. The output ripple in continuous mode will be
highest at the maximum input voltage. The output voltage
ripple due to ESR is approximately:
V
= R
ORIPPLE
ESR
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1736. These items are also illustrated graphically in
the layout diagram of Figure 10. Check the following in
your layout:
1. Are the signal and power grounds segregated? The
LTC1736 PGND pin should tie to the GND plane close to
the input capacitor. The SGND pin should then connect
to PGND and all components that connect to SGND
should make a single point tie to the SGND pin. The low
side FET source pins should connect directly to the
input capacitor ground.
LTC1736
= 80pF. At maximum input
RSS
[
2
+
°
12
1 0 005 50
( .
)(
C
–
25
2
V
12
A
80
pF
275
kHz
( ) ( )
(
1 6
V
2
12
A
1 1 0 0065
.
.
V
is chosen with an ESR of 0.01Ω for low
(∆I
) = 0.01Ω(5A) = 50mV
L
]
(
)
°
Ω
C
)
0 03
.
)
)
Ω
P-P
25
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