Linear Technology LTC1736 Datasheet page 16

LTC1736
APPLICATIO S I FOR ATIO
Table 1. VID Output Voltage Programming
VID4 VID3 VID2
0 0 0
0 0 0
0 0 0
0 0 0
0 0 1
0 0 1
0 0 1
0 0 1
0 1 0
0 1 0
0 1 0
0 1 0
0 1 1
0 1 1
0 1 1
0 1 1
1 0 0
1 0 0
1 0 0
1 0 0
1 0 1
1 0 1
1 0 1
1 0 1
1 1 0
1 1 0
1 1 0
1 1 0
1 1 1
1 1 1
1 1 1
1 1 1
Note: *, ** represents codes without a defined output voltage as specified in
Intel specifications. The LTC1736 interprets these codes as valid inputs and
produces output voltages as follows: [01111] = 1.250V, [11111] = 0.900V.
16
VID1 VID0 V (V)
OUT
0 0 2.000V
0 1 1.950V
1 0 1.900V
1 1 1.850V
0 0 1.800V
0 1 1.750V
1 0 1.700V
1 1 1.650V
0 0 1.600V
0 1 1.550V
1 0 1.500V
1 1 1.450V
0 0 1.400V
0 1 1.350V
1 0 1.300V
1 1 *
0 0 1.275V
0 1 1.250V
1 0 1.225V
1 1 1.200V
0 0 1.175V
0 1 1.150V
1 0 1.125V
1 1 1.100V
0 0 1.075V
0 1 1.050V
1 0 1.025V
1 1 1.000V
0 0 0.975V
0 1 0.950V
1 0 0.925V
1 1 **
Topside MOSFET Driver Supply (C
An external bootstrap capacitor C
pin supplies the gate drive voltage for the topside MOSFET.
Capacitor C in the Functional Diagram is charged though
B
external diode D from INTV
B
Note that the voltage across C
INTV . When the topside MOSFET is to be turned on, the
CC
driver places the C voltage across the gate-source of the
B
MOSFET. This enhances the MOSFET and turns on the
topside switch. The switch node voltage SW rises to V
and the BOOST pin rises to V
boost capacitor C needs to be 100 times greater than the
B
total input capacitance of the topside MOSFET. In most
applications 0.1µF to 0.33µF is adequate. The reverse
breakdown on D must be greater than V
B
When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If you make a change
and the input current decreases, then you improve the
efficiency. If there is no change in input current, then there
is no change in efficiency.
+ –
SENSE /SENSE Pins
The common mode input range of the current comparator
is from 0V to 1.1(INTV ). Continuous linear operation is
CC
guaranteed throughout this range allowing output volt-
ages anywhere from 0.8V to 7V (although the VID control
pins only program a 0.925V to 2.00V output range). A
differential NPN input stage is used and is biased with
internal resistors from an internal 2.4V source as shown
in the Functional Diagram. This causes current to flow out
of both sense pins to the main output. This forces a
minimum load current which is sunk by the internal
resistive divider resistors R1 and R2. The maximum
current flowing out of the sense pins is:
I SENSE + + I SENSE – = (2.4V – V
Remember to take this current into account if resistance is
placed in series with the sense pins for filtering.
, D )
B B
connected to the BOOST
B
when the SW pin is low.
CC
is about a diode drop below
B
+ INTV . The value of the
IN CC
IN(MAX) .
)/24k
OUT
IN