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Terasic MAX10-Plus User Manual

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MAX 10 Plus User
Manual
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www.terasic.com
May 31, 2019

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Summary of Contents for Terasic MAX10-Plus

  • Page 1 MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 2: Table Of Contents

    QSPI Flash ..........................25 3.4.9 Ethernet ..........................26 3.4.10 HDMI RX ..........................28 3.4.11 2x10 ADC Header ......................... 29 3.4.12 Potentiometer ......................... 30 3.4.13 On-board Microphone ......................30 3.4.14 PS/2 Serial Port ........................30 MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 3 6.7 Humidity/Temperature Sensor ....................77 Chapter 7 Programming the Configuration Flash Memory ........79 7.1 Internal Configuration ......................79 7.2 Using Dual Compressed Images....................81 7.3 Nios II Load In Single Boot Image ..................84 MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 4: Max 10 Plus Development Kit

    Chapter 1 MAX 10 Plus Development Kit The MAX 10 Plus board from Terasic is a full featured embedded evaluation kit based upon the MAX10 family of Intel FPGAs. It offers a comprehensive design environment with everything embedded developers need to create a processing-based system.

  • Page 5: Max 10 Plus System Cd

    Users can download this system CD from the link: http:// max10-plus.terasic.com/cd. 1.3 Getting Help Here are the addresses where you can get help if you encounter any problems: • Terasic Technologies • 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan Email: support@terasic.com Tel.: +886-3-575-0880 Website: max10-plus.terasic.com...

  • Page 6: Introduction Of The Max 10 Plus

    • USB-Blaster II onboard for programming; JTAG Mode • 256MB DDR3 SDRAM (64Mx16 and 128Mx8) • 64MB QSPI Flash • Micro SD card socket • Five push-buttons • Ten slide switches MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 7: Block Diagram Of The Max 10 Plus

    All the connections are established through the MAX 10 FPGA device to provide maximum flexibility for users. Users can configure the FPGA to implement any system design. Figure 2-2 Block Diagram of MAX 10 Plus Board MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 8 Communication and Expansion Header • Gigabit Ethernet PHY with RJ45 connector • UART to USB, USB Mini-B connector • PS/2 mouse/keyboard connector • 2x6 TMD (Terasic Mini Digital) Expansion Header Audio • 24-bit CD-quality audio CODEC with line-in, line-out jacks Video Input •...
  • Page 9 • Ten red user LEDs • Two 7-segment displays Sensors • Ambient light sensor • Humidity and temperature sensor • Accelerometer • Power monitor Power • 5V/3A DC input MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 10: Using The Max 10 Plus

    ◼ Configure the FPGA in JTAG Mode The following shows how the FPGA is programmed in JTAG mode step by step. 1. Open the Quartus II programmer and click Auto Detect, as circled in Figure 3-2. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 11 Figure 3-2 Detect FPGA Device in JTAG Mode 2. Select detected device associated with the board, as circled in Figure 3-3. Figure 3-3 Select 10M50DAES Device 3. FPGA is detected, as shown in Figure 3-4. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 12 4. Right click on the FPGA device and open the .sof file to be programmed, as highlighted in Figure 3-5. Figure 3-5 Open the .sof File to be Programmed into the FPGA Device MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 13 6. Click Program/Configure check box and then click Start button to download the .sof file into the FPGA device, as shown in Figure 3-7. Figure 3-7 Program. sof File into the FPGA Device MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 14: Board Status Elements

    In addition to the 10 LEDs that FPGA device can control, there are 4 indicators which can indicate the board status (See Figure 3-9), please refer the details in Table 3-1. Figure 3-9 LED Indicators on MAX 10 Plus MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 15: Clock Circuitry

    MAX CPLD of USB Blaster II. One 10MHz clock signal is connected to the PLL1 and PLL3 of FPGA, the outputs of these two PLLs can drive ADC clock. The associated pin assignment for clock inputs to FPGA I/O pins is listed in Table 3-2. MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 16: Peripherals Connected To The Fpga

    Schmitt trigger input on all I/O pins. A Schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity, especially for signal with slow edge rate and act as switch debounce in Figure 3-12 for the push-buttons connected. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 17 FPGA. When the switch is set to the DOWN position (towards the edge of the board), it generates a low logic level to the FPGA. When the switch is set to the UP position, a high logic level is generated to the FPGA. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 18 Figure 3-14 Connections between the LEDs and the MAX 10 FPGA Table 3-3 Pin Assignment of Push-buttons Signal Name FPGA Pin No. Description I/O Standard KEY[0] PIN_T22 Push-button[0] 1.5V KEY[1] PIN_U22 Push-button[1] 1.5V KEY[2] PIN_AA22 Push-button[2] 1.5V KEY[3] PIN_AA21 Push-button[3] 1.5V MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 19: 7-Segment Displays

    FPGA, respectively. Each segment in a display is indexed from 0 to 6, with corresponding positions given in Figure 3-15. Table 3-6 shows the pin assignment of FPGA to the 7-segment displays. MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 20: Power Monitor

    Table 3-7 shows the pin assignment of power monitor I2C bus. MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 21: 2X6 Tmd Expansion Header

    3.4.4 2x6 TMD Expansion Header The board has one 2x6 TMD (Terasic Mini Digital) expansion header. The TMD header has 8 digital GPIO user pins connected to the MAX 10 FPGA, two 3.3V power pins and two ground pins. There are two Transient Voltage Suppressor diode arrays used to implement ESD protection for 8 GPIO user pins.

  • Page 22: 24-Bit Audio Codec

    PIN_H12 Audio serial data bus (primary) word clock 2.5V AUDIO_DIN_MFP1 PIN_J13 Audio serial data bus data output/digital microphone output 2.5V AUDIO_DOUT_MFP2 PIN_H13 Audio serial data bus data input/general purpose input 2.5V AUDIO_SCLK_MFP3 PIN_H14 SPI serial Clock/headphone-detect output 2.5V MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 23: Two Analog Input Sma Connectors

    8bit (128Mx8) device. The DDR3 devices shipped with this board are running at 300MHz with the soft IP of MAX 10 external memory interface solution. Figure 3-20 shows the connections MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 24 SSTL-15 Class I DDR3_CKE PIN_V18 Clock Enable pin for DDR3 SSTL-15 Class I DIFFERENTIAL 1.5-V DDR3_CLK_n PIN_E18 Clock n for DDR3 SSTL Class I DDR3_CLK_p PIN_D18 Clock p for DDR3 Differential 1.5-V SSTL MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 25: Qspi Flash

    This device has a 4-bit data interface and uses 3.3V CMOS signaling standard. Connections between MAX 10 FPGA and Flash are shown in Figure 3-21. Table 3-11 shows the MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 26: Ethernet

    GMII/MII/RGMII/TBI MAC interfaces. Figure 3-22 shows the connections between the MAX 10 FPGA, Ethernet PHY, and RJ-45 connector. The pin assignment associated to Gigabit Ethernet interface is listed in Table 3-12. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 27 GMII and MII collision 2.5V NET_RX_CRS PIN_A9 GMII and MII carrier sense 2.5V NET_GTX_CLK PIN_C11 GMII Transmit Clock NET_LINK100 PIN_A7 Parallel LED output of 100BASE-TX link 2.5V NET_INT_n PIN_C13 Interrupt open drain output 2.5V MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 28: Hdmi Rx

    Video Pixel Output Port 3.3V HDMI_RX_D11 PIN_W14 Video Pixel Output Port 3.3V HDMI_RX_D12 PIN_V14 Video Pixel Output Port 3.3V HDMI_RX_D13 PIN_V15 Video Pixel Output Port 3.3V HDMI_RX_D14 PIN_U15 Video Pixel Output Port 3.3V MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 29: 2X10 Adc Header

    1 and pin 2 of J13 to select on-board microphone, short pin 3 and pin 4 to select pin 16 of 2x10 header J7. Figure 3-24 shows the connection of 2x10 ADC header and MAX 10 FPGA. MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 30: Potentiometer

    The pin assignment associated to this interface is shown in Table 3-14. Note: If users connect only one PS/2 equipment, the PS/2 signals connected to the FPGA I/O should be “PS2_CLK” and “PS2_DAT”. MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 31: Digital-To-Analog Converter (Dac)

    The analog voltage output of DAC8551 is connected to a SMA connector. Figure 3-27 shows the connection between DAC and MAX 10 FPGA. The pin assignment associated to this DAC is shown in Table 3-15. MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 32: Uart To Usb

    MAX 10 FPGA, FT232R chip, and the USB Mini-B connector. Table 3-16 lists the pin assignment of UART interface connected to the MAX 10 FPGA. Figure 3-28 Connections between the HPS and FT232R Chip MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 33: Ambient Light Sensor

    MAX 10 Plus. Figure 3-30 shows the connection of humidity and temperature sensor to MAX 10 FPGA. Table 3-18 lists the humidity and temperature sensor pin assignments. MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 34: Accelerometer Sensor

    MAX 10 FPGA and accelerometer. Table 3-19 lists the pin assignment of accelerometer to the MAX 10 FPGA. Figure 3-31 The Connections between the MAX 10 FPGA and Accelerometer Sensor MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 35: Micro Sd Card Socket

    PIN_A18 SD Data[1] 2.5V SD_DATA[2] PIN_B17 SD Data[2] 2.5V SD_DATA[3] PIN_C17 SD Data[3] 2.5V 3.4.21 Power Distribution System The MAX 10 Plus is powered by Linear Technology’s power solution which provides MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 36 FPGAs and SoCs. Figure 3-33 shows the power tree of MAX 10 Plus. Note that the LCD interface are reserved. Figure 3-33 Power Tree of MAX 10 Plus MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 37: The Max 10 Plus System Builder

    I/O standard for each user-defined I/O pin. These files can be modified according to the project requirements. After the compilation is successful, users can download the .sof file to the development board via JTAG interface using the Quartus II programmer. MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 38: Using Max 10 Plus System Builder

    Plus System CD. Users can copy the entire folder to a host PC without installing the utility. After the execution of the MAX 10 Plus SystemBuilder.exe on the host PC, a window will pop up, as shown in Figure 4-2. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 39 Figure 4-2 The GUI of MAX 10 Plus System Builder ◼ Enter Project Name The project name entered in the circled area, as shown in Figure 4-3, will be assigned automatically as the name of the top-level design entity. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 40 I/O standard. Note: The MIPI CS2 Camera and LCD Touch Panel interfaces are reserved, users can choose to buy MAX 10 NEEK instead if needed these two interfaces. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 41 ◼ Project Settings The MAX 10 Plus System Builder also provides the option to load a setting or save the current board configuration in .cfg file, as shown in Figure 4-5. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 42 When users press the Generate button, as shown in Figure 4-6, the MAX 10 Plus System Builder will generate the corresponding Quartus II files and documents, as listed in Table 4-1. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 43 Synopsis design constraints file for Quartus II <Project name>.htm Pin assignment document Users can add custom logic into the project and compile the project in Quartus II to generate the SRAM Object File (.sof). MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 44: Rtl Example Codes

    10ms time. The transmit data consists of 12bits, one start bit (as explained before), eight data bits, one parity check bit (odd check), one stop bit (always one), and one acknowledge bit (always zero). MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 45 ◼ Demonstration Source Code • Project directory: ps2_mouse • Bitstream used: ps2_mouse.sof ◼ Demonstration Batch File • Demo batch file folder: Demonstrations\ps2_mouse\demo_batch • Batch file: ps2_mouse.bat • FPGA configuration file: ps2_mouse.sof MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 46: Adc Potentiometer

    ADC hard IP block in MAX10 device. Figure 5-2 Block Diagram of ADC Hard IP Block This demo uses 2nd ADC of MAX10 on channel 8. The ADC settings are shown in Figure 5-3. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 47 MAX 10, so HEX1 and HEX0 shows the decimal point and the first digit after the decimal point respectively. Figure 5-4 Block Diagram of ADC Potentiometer ◼ Design Tools • Quartus II v15.0 64-bit MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 48: Dac Demonstration

    The analog signal coming out of the DAC SMA connector is connected to the oscilloscope and shown in square wave. Users can switch the SW0~2 to change the frequency of the square wave. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 49 • Switch SW [2:0] from 000 to 111 and the frequency of the square will be changing. The square-wave frequency is twice higher. When SW [2:0]=000, the square wave frequency is about 2.6KHz; When SW[2:0]=111, the frequency is about 112KHz. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 50 Figure 5-6 Use the Oscilloscope to Observe the Square Wave Figure 5-7 Probe DAC SMA OUT from the Oscilloscope MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 51: Adc/Mic/Led Demonstration

    12-bit to sign 16-bit etc. The module DAC16 converts the digitized signal in parallel to 16-bit serial format for the DAC chip (DAC8551) to the Line-out via audio codec (TLV320AIC3254). The module LED_METER displays the volume of the sound on the 8 LEDs onboard. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 52 OUT from the oscilloscope, or we can also connect external speaker to Line-out to hear the sound, as Figure 5-10. The volume of the sound from the MIC is displayed digitally on LEDR0~7, as Figure 5-11. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 53 Figure 5-10 The Waveform of onboard MIC is Displayed on the Oscilloscope. Its Sound is Played out from the Speaker Figure 5-11 LEDR0~7 Displays the Volume Level of onboard MIC MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 54: Nios Based Example Codes

    Nios II processor is running at 50MHz. The I2C library is located in the files named I2C_core.cpp and I2C_core.h. The I2C OpenCore IP is located in the folder “ip/i2c_opencores” under the project directory. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 55 This bit will be “set” i.e. 1 when the register content is renewed and “cleared” i.e. 0 when the register content is accessed. Bit 6 of the MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 56 (V1-V2). Bits b[2:0] should be set to ‘110’ for measuring voltage difference (V1-V2) and (V3-V4). Bits [4:3] should be set to 00 for all measurements. Figure 6-4 Control Register of LTC2990 MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 57 • Power on the MAX 10 Plus board. • Execute demo batch file “test.bat” under folder Demonstrations\power_monitor_nios\demo_batch. • Nios II terminal will display the measured power consumption measured, as shown in Figure MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 58: Uart To Usb Control Led

    The PLL generates a 100MHz clock for Nios II processor and the controller IP. The LEDRs are controlled by the PIO IP. The UART controller sends and receives command data and the command is sent through Putty terminal on the computer. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 59 • Nios II Program: uart_usb.elf ◼ Demonstration Setup Please follow the procedures below to set up the demonstration: • Connect a USB cable between your computer and the USB connector(J18) on MAX 10 Plus board. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 60 • Open the putty software, type in the parameter as shown in Figure 6-10 and click open button to open the terminal.(Here is a link for you to download the putty terminal: Download Putty) MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 61: Sd Card Audio Demonstration

    CF card, to store music or video files. Such players may also include high-quality DAC devices such that good audio quality can be produced. The MAX 10 Plus board provides the hardware and MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 62 SD Card socket. SD 4-Bit Mode is used to access the micro SD Card and is implemented by software. All the other SOPC components in the block diagram are SOPC Builder built-in components. The PIO pins are also connected to the keys, LEDs and switches. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 63 The Audio block implements audio FIFO checking function and audio signal sending/receiving function. The key and switch block acts as a control interface of the music player system. Figure 6-14 Software Stack of SD Card Audio Demo MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 64 SD Card in later. • Insert the micro SD card into the micro SD socket on MAX 10 Plus board. • Make sure Quartus II and Nios II are installed on your PC. MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 65: Ddr3 Sdram Test By Nios Ii

    150MHz for those host controllers, e.g. Nios II processor, accessing the SDRAM. In the Qsys, Nios II and the On-Chip Memory are designed running with the 100MHz clock, and the Nios II program is running in the on-chip memory. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 66 • Quartus Project directory: ddr3_nios • Nios II Eclipse Project workspace: ddr3_nios/software ◼ Nios II Project Compilation • Before you attempt to compile the reference design under Nios II Eclipse, make sure the project MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 67 • Press KEY4~KEY0 of the MAX 10 Plus board to start SDRAM verify process. Press KEY0 for continued test. • The program will display progress and result information, as shown in Figure 6-17. Figure 6-17 Display Progress and Result Information for the DDR3 Demo MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 68: Ethernet Socket Server

    JTAG UART, timer, Triple-Speed Ethernet, Scatter-Gather DMA controller and other peripherals etc. In the Core Configuration Tab of the Altera Triple-Speed Ethernet Controller, users need to set the MAC interface as RGMII as shown in Figure 6-19. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 69 MAC control register interface clock to produce the MDC clock output on the MDIO interface. The MAC control register interface clock frequency is 100MHz and the desired MDC clock frequency is 2.5MHz, so a host clock divisor of 40 should be used. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 70 Figure 6-20 MAC Options Configuration Once the Triple-Speed Ethernet IP configuration has been set and necessary hardware connections have been made as shown in Figure 6-21, click on generate. Figure 6-21 Qsys Builder MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 71 C/OS-II provides communication services to the NicheStack™ and the Socket Server. The NicheStack™ TCP/IP Stack software block provides networking services to the application block where it contains the tasks for Socket Server and also LED management. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 72 IP from the Gateway, or else you would need to reconfigure the system library to use static IP assignment. ◼ Design Tools • Quartus II v15.0 • Nios II Eclipse 15.0 MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 73 Figure 6-24 Simple Socket Server • To establish connection, start the telnet client session by executing open_telnet.bat file and include the IP address assigned by the DHCP server-provided IP along with the port number as MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 74 LEDRs (D0-D7) to toggle on or off on the MAX 10 Plus board as shown below in Figure 6-26. MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 75: Digital Accelerometer Demonstration

    Nios II processor and other components, and there is also 40MHz for low-speed peripherals. Figure 6-27 Block Diagram of the Digital Accelerometer Demonstration ◼ Demonstration Source Code • Project directory: gsensor_lightsensor • Bit stream used: gsensor_lightsensor.sof MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 76 • Tilt the MAX 10 Plus to all directions, and you will find that the angle of the g-sensor and value of light sensor will change. Figure 6-28 shows the demonstration result. Figure 6-28 Digital Accelerometer Demonstration Note: Execute gsensor_lightsensor_\demo_batch\gsensor_lightsensor.bat to download .sof and .elf files. MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 77: Humidity/Temperature Sensor

    DRDYn. In this demonstration, a delay in I2C function is adopted to simplify the process. ◼ Design Tools • Quartus II v15.0 • Nios II Eclipse 15.0 ◼ Demonstration Source Code • Quartus project directory: humidity_temperature • Nios II Eclipse project workspace: humidity_temperature \software MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 78 • Execute the demo batch file “humidity_temperature.bat” under the batch file folder, humidity_temperature\demo_batch. • NIOS terminal and will display the humidity and temperature values. Figure 6-30 shows the demonstration result. Figure 6-30 Humidity and Temperature Sensor Demo MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 79: Programming The Configuration Flash Memory

    In dual compressed images mode, you can use the BOOT_SEL pin to select the configuration image. The High-Level Overview of Internal Configuration for MAX 10 Devices as shown in Figure 7-1. Figure 7-1 High-Level Overview of Internal Configuration for MAX 10 Devices MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 80 5. Reconfiguration is triggered by the following actions: • Driving the nSTATUS low externally • Asserting internal or external nCONFIG low MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 81: Using Dual Compressed Images

    • Save the Qsys as dual_boot.qsys and generate the HDL files. Add the dual_boot.qip into the quartus setting file and add the qsys instance in the top design file as shown in Figure 7-4. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 82 • The next step is to convert the two sof files into a pof file for programming the MAX10 FPGA. Open the convert programming Files tool in Quartus and set as Figure 7-6. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 83 • The final step is to download the pof into MAX10 FPGA. Open the programmer tool and add the dual_boot.pof as shown in Figure 7-8. Click Start button to program the device when the hardware is set OK. Figure 7-8 Download the pof MAX 10 Plus User www.terasic.com Manual May 31, 2019...

  • Page 84: Nios Ii Load In Single Boot Image

    • In the BSP Editor (Nios II SBT for Eclipse) utility of the Eclipse, all the check box in the hal.linker table should be checked as shown in Figure 7-10. Figure 7-10 BSP Advance Setting MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 85 • Click the Options/Boot info… button. Choose the UFM source as the load memory file and click browse button to open the onchip flash hex file as shown in Figure 7-13. Press OK button to close the window. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 86 • Open the programmer tool and add the pof generated above to download into the onchip flash. Power cycle the board, the Nios II software will be running after the image has been loaded. MAX 10 Plus User www.terasic.com Manual May 31, 2019...
  • Page 87 Chapter 8 Appendix Revision History Version Change Log V1.0 Initial Version Copyright Statement Copyright ©Terasic Inc. All rights reserved. MAX 10 Plus User www.terasic.com Manual May 31, 2019...

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