Terasic Altera DE2i-150 Manual
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Terasic Altera DE2i-150 Manual

My first fpga
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  • Page 1 My First FPGA for Altera DE2i-150 Board...

  • Page 2: Table Of Contents

    CONTENTS Introduction Chapter 1  .......... 1  1.1 Design Flow ................1  1.2 Before You Begin ..............2  1.3 What You Will Learn ..............6  Assign The Device ........8  Chapter 2  2.1 Assign The Device ..............8  Design Entry ........12  Chapter 3 ...

  • Page 3: Introduction

    Chapter 1 Introduction This tutorial provides comprehensive information that will help you understand how to create a FPGA design and run it on you DE2i-150 development board. The following sections provide a quick overview of the design flow, explain what you need to get started, and describe what you will learn.

  • Page 4: Before You Begin

    This tutorial assumes the following prerequisites ■ You generally know what a FPGA is. This tutorial does not explain the basic concepts of programmable logic. ■ You are somewhat familiar with digital circuit design and electronic design automation (EDA) tools. ■...
  • Page 5 Figure 1-2 Connection Setup Figure 1-3 Found New Hardware Wizard Since the desired driver is not available on the Windows Update Web site, select “No, not this time” in response to the question asked and click Next. This leads to the window in Figure 1-4.
  • Page 6 Figure 1-4 The driver is found in a specific location The driver is available within the Quartus II software. Hence, select Install from a specific location and click Next to get to Figure 1-5. Figure 1-5 Specify the location of the driver Now, choose Search for the best driver in these locations and click Browse to get to the pop-up box Figure 1-6 Find the desired driver, which is at location C:\altera\12.0\quartus\drivers\usb-blaster.
  • Page 7 Figure 1-6 Browse to find the location Figure 1-7 There is no need to test the driver The driver will now be installed as indicated in Figure 1-8 Click Finish and you can start using the DE2i-150 board.

  • Page 8: What You Will Learn

    You don’t have to scour data books to find the perfect logic device or create your own ASIC. All you need is your computer, your imagination, and an Altera DE2i-150 FPGA development board.

  • Page 10: Assign The Device

    Chapter 2 Assign The Device You begin this tutorial by creating a new Quartus II project. A project is a set of files that maintain information about your FPGA design. The Quartus II Settings File (.qsf) and Quartus II Project File (.qpf) files are the primary files in a Quartus II project.
  • Page 11 What is the working directory for this project? Enter a directory in which you will store your Quartus II project files for this design. For example, E:\My_design\my_first_fpga. File names, project names, and directories in the Quartus II software cannot contain spaces. What is the name of this project? Type my_first_fpga.
  • Page 12 Figure 2-3 Specify the Device Example Click Finish. When prompted, choose Yes to create the my_first_fpga project directory. You just created your first Quartus II FPGA project. See Figure 2-4.
  • Page 13 Figure 2-4 my_first_fpga project...

  • Page 14: Design Entry

    Chapter 3 Design Entry This section describes How to Add a PLL Megafunction In the design entry step you create a schematic or Block Design File (.bdf) that is the top-level design. You will add library of parameterized modules (LPM) functions and use Verilog HDL code to add a logic block.
  • Page 15 Choose File > Save As and enter the following information.  File name: my_first_fpga  Save as type: Block Diagram/Schematic File (*.bdf) Click Save. The new design file appears in the Block Editor (see Figure 3-2). Figure 3-2 Bank BDF Add HDL code to the blank block diagram by choosing File >...
  • Page 16 Figure 3-3 Saving the Verilog HDL file The resulting empty file is ready for you to enter the Verilog HDL code. Type the following Verilog HDL code into the blank simple_counter.v file (see Figure 3-4 Verilog File of simple_counter.v). //It has a single clock input and a 32-bit output port module simple_counter ( CLOCK_50, counter_out...
  • Page 17 always @ (posedge CLOCK_50) // on positive clock edge begin counter_out <= #1 counter_out + 1;// increment counter endmodule // end of module counter Figure 3-4 The Verilog File of simple_counter.v Save the file by choosing File > Save, pressing Ctrl + s, or by clicking the floppy disk icon. 10.
  • Page 18 Figure 3-5 Create Symbol File was Successful 11. Click OK. 12. To add the simple_counter.v symbol to the top-level design, click the my_first_fpga.bdf tab. 13. Choose Edit > Insert Symbol. 14. Double-click the Project directory to expand it. 15. Select the newly created simple_counter symbol by clicking it’s icon. You can also double-click in a blank area of the BDF to open the Symbol dialog box Figure 3-6 Adding the Symbol to the BDF 16.
  • Page 19 Move the cursor to the BDF grid; the symbol image moves with the cursor. Click to place the simple_counter symbol onto the BDF. You can move the block after placing it by simply clicking and dragging it to where you want it and releasing the mouse button to place it. See Figure 3-7.
  • Page 20 pre-built LPM megafunction named ALTPLL. Choose Edit > Insert Symbol or click Add Symbol on the toolbar---　 Click Megawizard Plug-in Manager. The MegaWizard® Plug-In Manager appears (see Figure 3-8). Figure 3-8 Mega Wizard Plug-In Manager Click Next. In MegaWizard Plug-In Manager [page 2a], specify the following selections (see Figure 3-9): Choose I/O >...
  • Page 21 Figure 3-9 MegaWizard Plug-In Manager [page 2a] Selections In the MegaWizard Plug-In Manager [page 3 of 14] window, make the following selections (see Figure 3-10). Confirm that the Currently selected device family option shows the device family that corresponds to the development board you are using. The device speed grade choose 6 for DE2i-150.
  • Page 22 Figure 3-10 MegaWizard Plug-In Manager [page 3 of 14] Selections Turn off all options on MegaWizard page 4. As you turn them off, pins disappear from the PLL block’s graphical preview. See Figure 3-11 for an example.
  • Page 23 Figure 3-11 MegaWizard Plug-In Manager [page 4 of 14] Selections Click Next four times, In the MegaWizard Plug-In Manager [page 8 of 14] window, make the following selections (see Figure 3-12). 　 Clock Division Settings input 10...
  • Page 24 Figure 3-12 MegaWizard Plug-In Manager [page 8 of 14] Selections Click Next. 10. The wizard displays a summary of the files it creates (see Figure 3-13). Click Finish .
  • Page 25 Figure 3-13 Wizard-Created Files The Symbol window opens, showing the newly created PLL megafunction. See Figure 3-14.
  • Page 26 Figure 3-14 PLL Symbol 11. Click OK and place the pll symbol onto the BDF to the left of the simple_counter symbol. You can move the symbols around by holding down the left mouse button, helping you ensure that they line up properly.
  • Page 27 Figure 3-15 Place the PLL Symbol Move the mouse so that the cursor (also called the selection tool) is over the pll symbol’s c0 output pin. The orthogonal node tool (cross-hair) icon appears. Click and drag a bus line from the c0 output to the simple_counter clock input. This action ties the pll output to the simple_counter input (see Figure 3-16).
  • Page 28 Choose Edit > Insert Symbol. Under Libraries, select quartus/libraries > primitives > pin >input. See Figure 3-17 Click OK If you need more room to place symbols, you can use the vertical and horizontal scroll bars at the edges of the BDF window to view more drawing space. Figure 3-17 Input pin symbol Place the new pin onto the BDF so that it is touching the input to the pll symbol.
  • Page 29 Change the pin name by double-clicking pin_name and typing CLOCK_50 (see Figure 3-19). This name correlates to the oscillator clock that is connected to the FPGA. Using the Orthogonal Bus tool, draw a bus line connected on one side to the simple_counter output port, and leave the other end unconnected at about 4 to 8 grid spaces to the right of the simple_counter.
  • Page 30 Figure 3-20 Change the output BUS name Figure 3-21 BDF...

  • Page 31: Add A Multiplexer

    This design uses a multiplexer to route the simple_counter output to the LED pins on the DE2i-150 development board. You will use the MegaWizard Plug-In Manager to add the multiplexer, lpm_mux. The design multiplexes two variations of the counter bus to four LEDs on the DE2i-150 development board.
  • Page 32 Figure 3-22 Selecting lpm_mux Under How many ‘data’ inputs do you want? Select 2 inputs (default). Under How ‘wide’ should the data input and result output be? Select 4 (see Figure 3-23).
  • Page 33 Figure 3-23 lpm_mux settings Click Next. 10. Click Finish twice. The Symbol window appears (see Figure 3-24 for an example).
  • Page 34 Figure 3-24 lpm_mux Symbol 11. Click OK 12. Place the counter_bus_mux symbol below the existing symbols on the BDF. See Figure 3-25 Figure 3-25 Place the lpm_mux symbol 13. Add input buses and output pins to the counter_bus_mux symbol as follows:...
  • Page 35 Using the Orthogonal Bus tool, draw bus lines from the data1x[3..0] and data0x[3..0] Input ports to about 8 to 12 grid spaces to the left of counter_bus_mux. Draw a bus line from the result [3..0] output port to about 4 to 8 grid spaces to the right of counter_bus_mux.
  • Page 36 Figure 3-27 choose an output pin 16. Click OK. 17. Place this output pin so that it connects to the counter_bus_mux result [3..0] bus output line. 18. Rename the output pin as LEDG [3..0] as described in steps 13 c and d. (see Figure 3-28).

  • Page 37: Assign The Pins

    20. Place this input pin below counter_bus_mux. 21. Connect the input pin to the counter_bus_mux sel pin. 22. Rename the input pin as KEY [0] (see Figure 3-29). Figure 3-29 Adding the KEY [0] Input Pin You have finished adding symbols to your design. You can add notes or information to the project as text using the Text tool on the toolbar (indicated with the A symbol).
  • Page 38 Figure 3-30 Pin Planner Example In the Location column next to each of the six node names, add the coordinates (pin numbers) as shown in Table 3-1 for the actual values to use with your DE2i-150 board. Table 3-1 Pin Information Setting Pin Name FPGA Pin Location KEY[0]...

  • Page 39: Create A Default Timequest Sdc File

    Figure 3-31 Completed Pin Planning Example Now, you are finished creating your Quartus II design! Timing settings are critically important for a successful design. For this tutorial you will create a basic Synopsys Design Constraints File (.sdc) that the Quartus II TimeQuest Timing Analyzer uses during design compilation.
  • Page 40 Figure 3-32 Default SDC Naming the SDC with the same name as the top-level file except for the .sdc extension causes the Quartus II software to using this timing analysis file automatically by default. If you used another name, you would need to add the SDC to the assignments file list.

  • Page 41: Compile And Verify Your Design

    Chapter 4 Compile and Verify Your Design After creating your design you must compile it. Compilation converts the design into a bitstream that can be downloaded into the FPGA. The most important output of compilation is an SRAM Object File (.sof), which you use to program the device. The software also generates other report files that provide information about your code as it compiles.
  • Page 42 Figure 4-1 Compilation Message for project When compilation is complete, the Quartus II software displays a message. Click OK to close the message box. The Quartus II Messages window displays many messages during compilation. It should not display any critical warnings; it may display a few warnings that indicate that the device timing information is preliminary or that some parameters on the I/O pins used for the LEDs were not set.

  • Page 43: Program The Fpga Device

    Figure 4-2 Compilation Report Example After compiling and verifying your design you are ready to program the FPGA on the development board. You download the SOF you just created into the FPGA using the USB-Blaster circuitry on the board. Set up your hardware for programming using the following steps: Connect the power supply cable to your board and to a power outlet.
  • Page 44 Figure 4-3 Programmer Window Click Hardware Setup. If it is not already turned on, turn on the USB-Blaster [USB-0] option under currently selected hardware. See Figure 4-4. Figure 4-4 Hardware Setting Click Close.

  • Page 45: Verify The Hardware

    If the file name in the Programmer does not show my_first_fpga.sof, click Add File. Select the my_first_fpga.sof file from the project directory (see Figure 4-5). Figure 4-5 Downloading Complete Congratulations, you have created, compiled, and programmed your first FPGA design! The compiled SRAM Object File (.sof) is loaded onto the FPGA on the development board and the design should be running.
  • Page 46 counter (bits [24..21]). If other LEDs emit faintness light, Choose Assignments > Device. Click Device and Options. Figure 4-6. Figure 4-6 Device and Options Choose unused pins. Reserve all unused pins: Choose the As input tri-stated option. See Figure 4-7.
  • Page 47 Figure 4-7 Setting unused pins Click twice OK. In the Processing menu, choose Start Compilation. After the compile, Choose Tools > Programmer. Select the my_first_fpga.sof file from the project directory. Click Start. At this time you could find the other LEDs are unlighted.

  • Page 48: De2I-150 System Builder

    Chapter 5 DE2i-150 System Builder & &  Tel ：+886-3-5508800  Fax ：+886-3-5502860  Add：No.356, Sec. 1, Fusing E. Rd., JhuBei City , HsinChu County Taiwan 302-64  Email：sales@terasic.com / support@terasic.com...

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