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LVDS connector - CN3
Pin
Signal
Pin
Signal
1
GND
2
GND
3
LVDS_ODD_TX3+
4
LVDS_EVEN_TX3+
5
LVDS_ODD_TX3-
6
LVDS_EVEN_TX3-
7
LVDS_ODD_TX2+
8
LVDS_EVEN_TX2+
9
LVDS_ODD_TX2-
10
LVDS_EVEN_TX2-
11
LVDS_ODD_TX1+
12
LVDS_EVEN_TX1+
13
LVDS_ODD_TX1-
14
LVDS_EVEN_TX1-
15
LVDS_ODD_TX0+
16
LVDS_EVEN_TX0+
17
LVDS_ODD_TX0-
18
LVDS_EVEN_TX0-
19
GND
20
GND
21
LVDS_ODD_CLK+
22
LVDS_EVEN_CLK+
23
LVDS_ODD_CLK-
24
LVDS_EVEN_CLK-
25
GND
26
GND
27
LVDS_DDC_CLK
28
BKLT_EN
29
LVDS_DDC_DATA
30
eDP_BLT_CTRL
31
+3.3V
32
VDD_ON
33
SW_VDD_LVDS
34
SW_BACK_LVDS
35
SW_VDD_LVDS
36
SW_BACK_LVDS
37
SW_VDD_LVDS
38
SW_BACK_LVDS
39
GND
40
GND
41
GND
42
GND
43
GND
44
GND
45
---
46
---
47
---
48
---
49
+3.3V
50
GND
Modulated (PWM) regulations.
CCOMe-C30
CCOMe-C30 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by F.B. Copyright © 2019 SECO S.p.A.
The LVDS interface is available on a connector type HR A1014WVA-S-2x25P or equivalent
(2 x 25p, male, straight, P1, low profile, polarised) is provided, with the pin-out indicated in
the following table (different configurations are shown).
Mating connector: HR A1014H-2X25P with HR A1014-T female crimp terminals.
Alternative mating connector, MOLEX 501189-5010 with crimp terminals series 501334.
When building a cable for connection of LVDS displays, please take care of twist as tight as possible differential
pairs' signal wires, in order to reduce EMI interferences. Shielded cables are also recommended.
Here following the signals related to LVDS management:
LVDS_ODD_TX0+/ LVDS_ODD_TX0-: LVDS Odd Channel differential data pair #0.
LVDS_ODD_TX1+/ LVDS_ODD_TX1-: LVDS Odd Channel differential data pair #1.
LVDS_ODD_TX2+/ LVDS_ODD_TX2-: LVDS Odd Channel differential data pair #2.
LVDS_ODD_TX3+/ LVDS_ODD_TX3-: LVDS Odd Channel differential data pair #3.
LVDS_ODD_CLK+/LVDS_ODD_CLK-: LVDS Odd Channel differential Clock.
LVDS_EVEN_TX0+/ LVDS_EVEN_TX0-: LVDS Even Channel differential data pair #0.
LVDS_EVEN_TX1+/ LVDS_EVEN_TX1-: LVDS Even Channel differential data pair #1.
LVDS_EVEN_TX2+/ LVDS_EVEN_TX2-: LVDS Even Channel differential data pair #2.
LVDS_EVEN_TX3+/ LVDS_EVEN_TX3-: LVDS Even Channel differential data pair #3.
LVDS_EVEN_CLK+/LVDS_EVEN_CLK-: LVDS Even Channel differential Clock.
LVDS_DDC_DAT: DisplayID DDC Data line for LVDS flat Panel detection. Bidirectional signal, electrical level
ll-up resistor.
LVDS_DDC_CLK: DisplayID DDC Clock line for LVDS flat Panel detection. Bidirectional signal, electrical level
-up resistor.
BKLT_EN: +3.3V electrical level Output, Backlight Enable signal. It can be used to turn On/Off the backlight's
lamps of connected displays.
VDD_ON: +3.3V electrical level Output, Panel Power Enable signal. It can be used to turn On/Off the connected
display.
eDP_BLT_CTRL: this signal can be used to adjust the backlight brightness in displays supporting Pulse Width
59
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