Trigger Circuit; Sweep Logic Circuit - Tektronix 2212 Service Manual

Horizontal System and Z-Axis Circuit
Trigger Circuit
Sweep Logic
Circuit
3- 14
0
The kernel of the trigger circuit is U400. This integrated circuit includes
two multiplexers, a comparator with schmitt trigger inputs and a control
unit.
The control unit U400A receives control data from the data chain U800
and vertical logic U810 (diagram 8) and controls the trigger circuit. The
trigger circuit is designed with two registers, one is latched with signal STB,
the other is transparent. The transparent register controls multiplexer 1,
U400B. This multiplexer performs the trigger source selection. CHl, CH2,
line, external, DT_Trig. The latter is a trigger signal generated by the system
processor. The latched register controls multiplexer 2, U400C. This multi-
plexer is used for trigger coupling selection (DC, AC, Low Frequency Reject,
High Frequency Reject, TV Field). When TV Field trigger mode is selected
on the front panel, the instrument operates in peak-peak auto mode (P-P
AUTO), combined with the TV sync. separator selected for trigger coupling.
The trigger signal is passed on to comparator U400D, also controlled by
U400A. U400D has a slope control for positive and negative slope trigger-
ing and a hysteresis control. In Noise Reject coupling, the hysteresis is
increased by a factor of 4. U400D compares the trigger signal with the
trigger level and generates the trigger pulses on ECL level. The trigger pulses
are passed on to the sweep logic. The trigger signal is also passed on to the
PEAK+ and PEAK- detectors. The outputs of these detectors have an offset
of 2.5 V and range from Oto +5 V. The output signals are processed by the
main processor. The calibration of the trigger circuit is performed in the
software.
The sweep logic is mainly inside PAL U500. PAL U500 contains logic for
X-Y-mode, single sweep mode, normal mode and P-P Auto with the auto
baseline logic.
Trigger pulses from diagram 4 are clocked into U502B. If sweep is not
disabled, the flip flop is set to '1' and the sweep gate becomes active,
starting the sweep in diagram 5B. When in auto mode and no trigger pulses
are generated, U500 sets U502B with the AUTOSTRT signal. U502A and
U504A are the trigger detector circuits.
U504 is a re-triggerable one-shot.
As
long as trigger pulses are produced, the
ATIME signal stays active high and the TRIGD_0 signal stays low. At the
end of the sweep, EOS becomes active high and U500 generates the
HOST ART (hold off start) pulse.
The HOST ART pulse starts the hold off generator (U504B ). The hold off
pulse resets the sweep gate and the trigger detect circuit U502. The hold off
pulse is also used as a clock signal for the horizontal and vertical logic,
U501 and U810. During hold off and in single sweep, but before SS-RESET,
SWPDIS_0 is active low. This prevents U502A and-B to be set, so no sweep
is started and no trigger pulses are detected. When a new code is loaded
into the serial data chain, the CHAIN_LD pulse will activate U500 to gener-
ate a HOST ART pulse, terminating the current sweep and starting a new
one with the new scope settings.
Theory of Operation