Acquisition System; Tµe, Acquisition Data ;Path; Referen~ Voltage 1 - Tektronix 2212 Service Manual

Acquisition System
c0
and
0)
2212
Service Manual
Digital Circuitry
The 16V8 PAL U1909 in combination with counter U1908 and flip-flop's
U1907 performs the FIFO "bookkeeping". It requests DMA's from the 68070
by driving REQ1_0 low until it reaches the "almost full" condition. This
results in a maximum number of words in the FIFO of 15 (for safety
purposes). The condition "FULL" (pin 14) should therefore never occur (this
output is added for debugging purposes only).
The output "EMPTY" is used by the 68070 to be able to check if a display
frame is completely finished.
Data is basically written on the CRT on a 50 Hz rate. One display cycle starts
with a pulse on the FIFORST line to make sure the hardware is reset. After
that, the first readout controlbyte is written in latch U1906 and the first DMA
transfer is started.
As
soon as the first DMA burst is fully accepted by the
FIFO's, an internal interrupt will automatically set the next readout control
byte and start the following DMA transfer, etc .. After having sent all DMA
transfers of one display frame, the processor will synchronize with the next
20 ms pulse.
The Acquisition Data Path
AID
Converters
Digitizing the input signals is done by the analog-to-digital converters
U1601 and U1602. Each channel has its own converter. The AID converters
are high speed flash converters producing an 8-bit digital word which
represents the magnitude of the analog input signal (pin 14). Conversion
takes place on the falling edge of CLK (CONVCLK). The range of the analog
input signal is +1 V to -1 V producing byte values of 11111111 to respectively
00000000.
Conversions are continuously taking place at the CONVCLK rate. When the
fastest range available in STORE mode (20 µsec/div) is selected, CONVCLK
runs at 20 MHz. On all other SEC/DIV settings, the A/D clock runs at 8 MHz
(see Timebase Table 3-3).
Reference Voltage
The sensitivity of the a/d converters is determined by a stable +1 V and-1
V
(applied to pins 24 and 23 respectively) voltage source. The analog +5 V
supply (+5VA1) supplies an input of 5 V to the inverting operational
amplifier U1600B. Resistors R1604 and R1603 set the gain, giving an output
of -1 Vat the emitter of Q1601. This transistor provides the current necessary
to drive the reference chain.
The +1 Vis generated in a similar fashion by unity-gain inverting amplifier
U1600C. The gain is set by the resistors R1601 and R1602 with Q1600
providing the current source requirements. Capacitors C1600 and C1603 limit
the bandwidth of the amplifiers for stability reasons.
3- 25