Swj Debug Port Pins; Flexible Swj-Dp Pin Assignment; Table; Debug Port Pin Assignment - ST STM32L152-EVAL Application Note

AN3216
5.3.1

SWJ debug port pins

Five pins are used as outputs for the SWJ-DP as alternate functions of general-purpose
I/Os (GPIOs). These pins, shown in

Table 2.

SWJ-DP pin name
JTMS/SWDIO
JTCK/SWCLK
JTDI
JTDO/TRACESWO
JNTRST
5.3.2

Flexible SWJ-DP pin assignment

After reset (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as
dedicated pins which are immediately usable by the debugger host (note that the trace
outputs are not assigned except if explicitly programmed by the debugger host).
However, the STM32L1xxx MCU implements a register to disable all or part of the SWJ-DP
port, and so releases the associated pins for general-purpose I/O usage. This register is
mapped on an APB bridge connected to the Cortex™-M3 system bus. It is programmed by
the user software program and not by the debugger host.
Table 3 shows the different possibilities for releasing some pins.
Table 3.
Full SWJ (JTAG-DP + SW-DP) - reset state
Full SWJ (JTAG-DP + SW-DP) but without
JNTRST
JTAG-DP disabled and SW-DP enabled
JTAG-DP disabled and SW-DP disabled
For more details, see the STM32L15xx reference manual (RM0038).

Debug port pin assignment

JTAG debug port
Type Description
JTAG test mode
I
selection
I JTAG test clock
I JTAG test data input
O JTAG test data output
I JTAG test nReset

SWJ I/O pin availability

Available debug ports
Doc ID 17496 Rev 5
Table 2, are available on all packages.
SW debug port
Type Debug assignment
Serial wire data
I/O
input/output
I Serial wire clock
- -
TRACESWO if async trace
-
is enabled
- -
SWJ I/O pin assigned
PA13 / PA14 /
JTMS/ JTCK/
SWDIO SWCLK
X X
X X
X X
Debug management
PA15 / PB3 /
JTDI JTDO
X X
X X
Released
Pin
assignment
PA13
PA14
PA15
PB3
PB4
PB4/
JNTRST
X
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