STEP CLOCK
3
4
5
2
6
8
7
1
Figure 1.2.3: Wave Mode Phase Sequence
H a l f S t e p M o d e
In half step mode the phasing alternates from one phase energized to two
phases energized. Half step mode is selected by a logic LOW on the Half/
Full step input.
3
4
5
STEP CLOCK
2
6
8
7
1
T i m i n g
STEP CLOCK
CW/CCW
HALF/FULL STEP
2
4
6
8
PHASE A
PHASE A
PHASE B
PHASE B
1
2
3
4
PHASE A
PHASE A
PHASE B
PHASE B
Figure 1.2.4: Half Step Mode
t
CLK
t
t
S
H
Figure 1.2.5: Timing
2
4
6
8
2
5
6
7
8
1
Parameter
Minimum
t
- Clock Time.......................3µs
CLCK
t - Set up time...........................2µs
S
t - Hold Time..............................5.5µs
H
13
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