Shuttle FX43G User Manual page 63

CPU & PCI Bus Control
Press <Enter> to enter the sub-menu of detailed options.
PCI1/PCI2 Master 0 WS Write
Enable this item to write to the PCI bus with zero wait executed state.
Ø The Choice: Enabled or Disabled.
PCI1/PCI2 Post Write
Enable this item to write to the PCI bus with post wait executed state.
Ø The Choice: Enabled or Disabled.
VLink 8X Support
This item enables or disables the VLink 8X support.
Ø The Choice: Enabled or Disabled.
PCI Delay Transaction
This item allows disables the PCI delay transaction.
Memory Hole
You can reserve this area of system memory for ISA adapter ROM. When
this area is reserved, it can't be cached. The user information of peripher-
als that need to use this area of system memory usually discusses their
memory requirements.
Ø The Choice: Disabled or 15M-16M.
System BIOS Cacheable
Select Enabled allows caching of the system BIOS ROM at F000h-FFFFFh,
resulting in better system performance. However, if any program is writ-
ten to this memory area, a system error may result.
Ø The Choice: Enabled or Disabled.
Video RAM Cacheable
Select Enabled allows caching of the video BIOS, resulting in better sys-
tem performance. However, if any program is written to this memory area,
a sysem error may result.
Ø The Choice: Enabled or Disabled.
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