Shuttle FX43G User Manual page 61

Amd athlon xp/athlon/duron 462-pin processor with 200/266/333 mhz fsb based ddr mainboard
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Bank Interleave
Not disable this item to increase SDRAM memory speed since separate
memory banks are set for odd and even addresses and the next byte of
memory can be accessed while the current byte is being refreshed.
Ø The Choice: Disabled, 2 Bank, or 4 Bank.
Precharge to Active(Trp)
This item defines the numbers of cycles for RAS (row address strobe) to be
allowed to precharge.
Ø The Choice: 2T, 3T, 4T, or 5T.
Active to Precharge(Tras)
The precharge time is the number of cycles it takes for DRAM to accu-
mulate its charge before refresh.
Ø The Choice: 8T, 7T, 6T, or 5T.
Active to CMD(Trcd)
This item defines the timing of the transition from RAS (row address strobe)
to CAS (column address strobe) as both rows and columns are separately
addressed shortly after DRAM is refreshed.
Ø The Choice: 2T, 3T, 4T, or 5T.
DRAM Burst Length
This item allows you to select the DRAM burst length.
Ø The Choice: 4 or 8.
DRAM Command Rate
This item allows you to select the DRAM executed rate.
Ø The Choice: 2T Command or 1T Command.
Write Recovery Time
This item allows you to select the DRAM writing recovery time.
Ø The Choice: 2T or 3T.
AGP & P2P Bridge Control
Press <Enter> to enter the sub-menu of detailed options.
AGP Aperture Size
Select the size of Accelerated Graphics Port (AGP) aperture. The aper-
ture is a portion of the PCI memory address range dedicated to graphics
memory address space. Host cycles that hit the aperture range are
forwarded to the AGP without any translation.
Ø The Choice: 4M, 8M, 16M, 32M, 64M, 128M, 256M, 512M, or 1G.
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