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~I~B;!l16i
_ Toe RAM INFORMATION
_~
Appendix B contains tables defining the TOe RAM locations displayed on the system console during
self test execution.
Toe RAM DA T A AND ST A TUS TABLES
Table 8-1. TOe RAM Data and Status
Toe
RAM ADDRESS
ST A TUS AND OAT A STORED IN TOC
RAM
ADDRESS
$OA
Register A
SOB
Register B
SOC
Register
e
SOD
Register
D
$OE
Undefined
$OF
Console ATP port 0 interrupt time-out flag*
$10
Last stop information. See Table 8-
2.
S 11
Sta rt device
S12
Load device
$13
Undefined
$14
Test loop counter (lower byte)
SI5
Test loop counter (upper byte)
SI6-S3F
Undefined
*
If the A TP port 0 interrupt time -out flag is set (contains
SAA)
this means port 0 of the ATP
in slot 1 of the SPU has failed to produce an expected interrupt within 500 milliseconds and the
microcode has timed-out. This flag should be checked if the RUN command cannot be executed.
If the flag is set, port 0 configuration information was not stored and thus could not be restored
upon executing the RUN command.
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