Layout Recommendation; Product Portfolio Of Coolset ® -F3R (Dip-8, Dip-7 & Dso-16/12) New Jitter Version - Infineon CoolSET-F3R ICE3BRXX65JZ series Design Manual

Dip-8, dip-7 & dso-16/12 new jitter version
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The major assumption for the calculation is listed below.
1. Reflection voltage from secondary side to primary side is 100V.
2. The maximum power for the device is estimated when the junction temperature of the integrated
®
CoolMOS
reaches 125°C. (With some margins to reach the over temperature protection of the
device : 130°C). The maximum R
3. There is no copper area as heatsink and the R
R
=110K/W for DSO-16/12.
thja
4. Saturation current (I
rectifier is assumed to be 1V. The typical resistance of the EMI filter is estimated for different
CoolSET. Those parameters are listed in the below table
ICE3BR0665J(Z)
ICE3BR1765J(Z)
ICE3BR4765J(Z)(G)
8

Layout Recommendation

In order to get the optimized ruggedness of the IC to the transient surge events like ESD and lightning Surge
test, the grounding of the PCB layout must be connected carefully. From the circuit diagram in Figure 5, it
indicates that the grounding for the controller can be split into several groups; signal ground, Vcc ground,
Current sense resistor ground and EMI return ground. All the split grounds should be "star" connected to the
bulk capacitor ground directly. The split grounds are described as below.
Signal ground includes all small signal grounds connecting to the controller GND pin such as filter
capacitor ground, C6, C7, C8 and opto-coupler ground.
Vcc ground includes the Vcc capacitor ground, C5 and the auxiliary winding ground, pin 2 of the power
transformer.
Current Sense resistor ground includes current sense resistor R4 and R4a.
EMI return ground includes Y capacitor, C4.
9
Product portfolio of CoolSET
new Jitter version
Device
ICE3BR0665J
ICE3BR1765J
ICE3BR4765J
ICE3BR0665JZ
ICE3BR1765JZ
ICE3BR4765JZ
ICE3BR4765JG
1
Tj=110°C
2
Typ @ 25°C
3
Calculated maximum input power rating at T
for other T
a
Application Note
of the device at 125°C is taken for calculation.
dson
@ 125°C) of the MOSFET is considered. The voltage drop for the bridge
d_max
Rdson_125°C (Ω)
1.58
4.12
12.5
1
Package
V
DS
PG-DIP-8
650V
PG-DIP-8
650V
PG-DIP-8
650V
PG-DIP-7
650V
PG-DIP-7
650V
PG-DIP-7
650V
PG-DSO-16/12
650V
=50°C, T
=125°C and without copper area as heat sink. Refer to the input power curve
a
j
=90K/W for DIP-8, R
thja
I
@125°C (A)
d_max
9.95
4.03
1.67
®
-F3R (DIP-8, DIP-7 & DSO-16/12)
2
Frequency
R
/Ω
dson
/ kHz
65
0.65
65
1.70
65
4.70
65
0.65
65
1.70
65
4.70
65
4.70
20
ICE3BRXX65J(Z)(G)
=96K/W for DIP-7 &
thja
R
(Ω)
V
EMI_filter
F_bridge
2 * 0.56
2 * 1
2 * 1
2 * 1
2 * 3
2 * 1
P
P
in
in
3
85-265Vac
230Vac±15%
49W
74W
31W
46W
18W
27W
47W
71W
29.5W
44.5W
18W
26W
16.5W
24W
(V)
3
2010-06-20

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