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Altera MAX 10 User Manual

Altera MAX 10 User Manual

Analog to digital converter
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MAX 10 Analog to Digital Converter User
Guide
Last updated for Quartus Prime Design Suite: 16.0
UG-M10ADC
101 Innovation Drive
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2016.05.02
San Jose, CA 95134
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www.altera.com

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  • Page 1 MAX 10 Analog to Digital Converter User Guide Last updated for Quartus Prime Design Suite: 16.0 UG-M10ADC 101 Innovation Drive Subscribe 2016.05.02 San Jose, CA 95134 Send Feedback www.altera.com...

  • Page 2: Table Of Contents

    Creating MAX 10 ADC Design........................4-2 Customizing and Generating Altera Modular ADC IP Core..............4-3 Parameters Settings for Generating ALTPLL IP Core................4-3 Parameters Settings for Generating Altera Modular ADC or Altera Modular Dual ADC IP Core................................4-5 Completing ADC Design..........................4-8 Altera Corporation...
  • Page 3 Altera Modular ADC and Altera Modular Dual ADC IP Cores References..5-1 Altera Modular ADC Parameters Settings....................5-2 Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping..5-6 Altera Modular Dual ADC Parameters Settings..................5-8 Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping.............................5-12...

  • Page 4: Max 10 Analog To Digital Converter Overview

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 5: Adc Block Counts In Max 10 Devices

    How to Create Simultaneous Measurement with MAX 10 ADC, Part 2 • Provides the second part of video instruction series that explains the differences between the MAX 10 Altera Modular ADC and Altera Modular Dual ADC IP cores. The video also demonstrates how to create a simple simultaneous ADC measurement and how to place signal taps to measure the digital code output for analog signal.

  • Page 6: Adc Channel Counts In Max 10 Devices

    2016.05.02 ADC Channel Counts in MAX 10 Devices Different MAX 10 devices support different number of ADC channels. Table 1-2: ADC Channel Counts in MAX 10 Devices • Devices with two ADC blocks have two dedicated analog inputs and each ADC block has 8 dual function pins.

  • Page 7: Max 10 Adc Vertical Migration Support

    MAX 10 ADC Vertical Migration Support 2016.05.02 MAX 10 ADC Vertical Migration Support Figure 1-1: ADC Vertical Migration Across MAX 10 Devices The arrows indicate the ADC migration paths. The devices included in each vertical migration path are shaded. Package...

  • Page 8: Max 10 Single Or Dual Supply Devices

    3.0 V or 3.3 V, depending on your power supply voltage. • In prescaler mode, the analog input can measure up to 3.0 V in dual supply MAX 10 devices and up to 3.6 V in single supply MAX 10 devices.
  • Page 9 Input Voltage (V) The MAX 10 ADC is a 1 MHz successive approximation register (SAR) ADC. If you set up the PLL and Altera Modular ADC IP core correctly, the ADC operates at up to 1 MHz during normal sampling and 50 kHz during temperature sensing.

  • Page 10: Max 10 Adc Architecture And Features

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 11: Adc Block Locations

    Altera Modular ADC IP Core ADC V Internal V ADC Block Locations The ADC blocks are located at the top left corner of the MAX 10 device periphery. Figure 2-2: ADC Block Location in MAX 10 04 and 08 Devices ADC1 I/O Bank...
  • Page 12 UG-M10ADC ADC Block Locations 2016.05.02 Figure 2-3: ADC Block Location in MAX 10 16 Devices ADC1 I/O Bank ADC Block MAX 10 ADC Architecture and Features Altera Corporation Send Feedback...

  • Page 13: Single Or Dual Adc Devices

    • You can use the dual function pins as GPIO pins when you do not use the ADC. Note: MAX 10 devices in the E144 package have only 8 dual function ADC pins. For devices with two ADC blocks, you can use up to 18 ADC channels: •...

  • Page 14: Adc Analog Input Pins

    The ADC block uses the device PLL as the clock source. The ADC clock path is a dedicated clock path. You cannot change this clock path. Depending on the device package, the MAX 10 devices support one or two PLLs—PLL1 only, or PLL1 and PLL3.

  • Page 15: Adc Voltage Reference

    ADC Temperature Sensing Diode The ADC block in MAX 10 devices has built-in TSD. You can use the built-in TSD to monitor the internal temperature of the MAX 10 device. • While using the temperature sensing mode, the ADC sampling rate is 50 kilosamples per second during temperature measurement.
  • Page 16 -13 3751 21 3684 55 3610 89 3526 123 3440 -12 3750 22 3682 56 3607 90 3525 124 3432 -11 3748 23 3680 57 3604 91 3524 125 3431 MAX 10 ADC Architecture and Features Altera Corporation Send Feedback...

  • Page 17: Adc Sequencer

    Guidelines: ADC Sequencer in Altera Modular Dual ADC IP Core Follow these sequencer guidelines if you use dual ADC blocks with the Altera Modular Dual ADC IP core. • The conversion sequence length of both ADC blocks must be the same.

  • Page 18: Adc Timing

    • Altera Modular Dual ADC IP core—you can control both ADC hard IP block with a single IP instance. • For the analog input pins (ANAIN1 and ANAIN2) in both ADC hard IP blocks, the measurement is synchronous.

  • Page 19: Altera Modular Adc Ip Core Configuration Variants

    2-10 Altera Modular ADC IP Core Configuration Variants 2016.05.02 You can perform the following functions with the Altera Modular ADC or Altera Modular Dual ADC IP core parameter editor: • Configure the ADC clock, sampling rate, and reference voltage. • Select which analog input channels that the ADC block samples.
  • Page 20 When the threshold value is violated, the Altera Modular ADC or Altera Modular Dual ADC IP core notifies the discrete logic component. The discrete component then triggers system recovery action. For example, the system can increase the fan speed in a temperature control system.
  • Page 21 Related Information • Customizing and Generating Altera Modular ADC IP Core on page 4-3 • Completing ADC Design on page 4-8 MAX 10 ADC Architecture and Features Altera Corporation Send Feedback...
  • Page 22 4-8 Configuration 4: ADC Control Core Only In this configuration variant, the Altera Modular ADC generates only the ADC control core. You have full flexibility to design your own application-specific sequencer and use your own way to manage the ADC samples.
  • Page 23 (clock from dedicated PLL) peripheral reset adc_pll_locked altera_adc_control (locked signal from dedicated PLL) command response Figure 2-14: ADC Control Core Only (Altera Modular Dual ADC IP Core) altera_dual_adc altera_adc_control response command peripheral clock adc_pll_clock peripheral reset (clock from dedicated PLL)

  • Page 24: Altera Modular Adc And Altera Modular Dual Adc Ip Cores Architecture

    Violation Detection Dual ADC synchronizer This core performs synchronization handshakes between two ADC control core cores. This core is available only if you use the Altera Modular Dual ADC IP core. MAX 10 ADC Architecture and Features Altera Corporation Send Feedback...
  • Page 25 The ADC control core drives the ADC hard IP according to the command it receives. The control core also maps the channels from the Altera Modular ADC IP core to the channels in the ADC hard IP block. The ADC control core of the Altera Modular ADC IP core implements only the functions that are related to ADC hard IP block operations.
  • Page 26 During Altera Modular ADC or Altera Modular Dual ADC IP core configuration, the sequencer core provides up to 64 configurable slots. You can define the sequence that the ADC channels are sampled by selecting the ADC channel for each sequencer slot.
  • Page 27 Lists the parameters available during Altera Modular ADC IP core configuration. • Altera Modular Dual ADC Parameters Settings on page 5-8 Lists the parameters available during Altera Modular Dual ADC IP core configuration. • Sequencer Core Registers on page 5-18 Lists the registers for run-time control of the sequencer core.
  • Page 28 The response merge core merges simultaneous responses from two ADC control cores in the Altera Modular Dual ADC IP core. The Altera Modular Dual ADC IP core uses the response merge core if you use the following configura‐ tions: • Standard Sequencer with Avalon-MM Sample Storage •...

  • Page 29: Altera Adc Hal Driver

    Modular Dual ADC IP core. However, the ADC Toolkit can only monitor one ADC block at a time. If you are using the Altera Modular Dual ADC IP core, configure the Debug Path parameter in the IP core to select which ADC block you want to hook up to the ADC Toolkit.

  • Page 30: Fixed Adc Logic Simulation Output

    UG-M10ADC 2-21 Fixed ADC Logic Simulation Output 2016.05.02 The ADC simulation model for MAX 10 devices supports the standard digital logic simulators that the Quartus Prime software supports. Related Information Quartus Prime Simulator Support Fixed ADC Logic Simulation Output In the default option (Disabled), the ADC simulation always output a fixed value for each ADC channel, including the analog and TSD channels.

  • Page 31: User-Specified Adc Logic Simulation Output

    (No TSD in ADC2) User-Specified ADC Logic Simulation Output You can configure the Altera Modular ADC or Altera Modular Dual ADC IP core to use expected output files that you provide for the logic simulation output for each ADC channel. The user-specified expected output file is not supported on the TSD channel.
  • Page 32 Voltage values (Hexadecimal) 0x164 0x2C8 0x37A Simulation 0x643 Sequence pattern: time flow 0x591 CH0, CH1, CH0, CH1... 0x90B 0x7A7 0xA6F × 2 0x9BD SIM_FILE_CH1 0xF4E Pattern repeats 0x164 0x2C8 = 2.3 V MAX 10 ADC Architecture and Features Altera Corporation Send Feedback...

  • Page 33: Max 10 Adc Design Considerations

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 34: Guidelines: Board Design For Analog Input

    • If you reduce the total sampling rate, you can calculate the required settling time as 0.45 ÷ F > 10.62 × RC constant • To gain more total RC margin, Altera recommends that you set the driver source impedance as low as possible: • For prescaler-disabled channel—less than 1 kΩ...
  • Page 35 • A low pass RC filter can reduce the trace spacing between analog input signal and digital I/O signal to meet -100 dB crosstalk requirement. Altera recommends that you place an active low pass filter to help in meeting the required settling time.

  • Page 36: Guidelines: Board Design For Adc Reference Voltage Pin

    REFGND REFGND There is one ADC reference voltage pin in each MAX 10 device. This pin uses as ground REFGND reference. Keep the trace resistance less than 0.8 Ω.

  • Page 37: Max 10 Adc Implementation Guides

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 38: Creating Max 10 Adc Design

    2-20 Creating MAX 10 ADC Design To create your ADC design, you must customize and generate the ALTPLL and Altera Modular ADC IP cores. The ALTPLL IP core provides the clock for the Altera Modular ADC IP core.

  • Page 39: Customizing And Generating Altera Modular Adc Ip Core

    2016.05.02 Customizing and Generating Altera Modular ADC IP Core Altera recommends that you use the Altera Modular ADC IP core with a Nios II processor, which supports the ADC HAL driver. 1. Create a new project in the Quartus Prime software.
  • Page 40 • on page 4-8 MAX 10 Clock Networks and PLLs User Guide • ADC PLL Clock Interface of Altera Modular ADC and Altera Modular Dual ADC • on page 5-17 • ADC PLL Locked Interface of Altera Modular ADC and Altera Modular Dual ADC on page 5-18 •...

  • Page 41: Parameters Settings For Generating Altera Modular Adc Or Altera Modular Dual Adc Ip Core

    Parameters Settings for Generating Altera Modular ADC or Altera Modular Dual ADC IP Core Navigate through the Altera Modular ADC IP core parameter editor and specify the settings required for your design. After you have specified all options as listed in the following tables, you can generate the HDL files and the optional simulation files.
  • Page 42 After it completes the temperature reading, the ADC sampling rate returns to 1 MHz. For the Altera Modular Dual ADC IP core, if you specify the TSD in a sequencer slot for ADC1, specify NULL in the same sequencer slot number for ADC2.
  • Page 43 5-8 • Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping on page 5-6 Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping • on page 5-12 Valid ADC Sample Rate and Input Clock Combination •...

  • Page 44: Completing Adc Design

    Completing ADC Design 2016.05.02 Completing ADC Design The ADC design requires that the ALTPLL IP core clocks the Altera Modular ADC IP core. Before you begin Generate the ALTPLL and Altera Modular ADC IP cores with the settings in the related information.

  • Page 45: Altera Modular Adc And Altera Modular Dual Adc Ip Cores References

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 46: Altera Modular Adc Parameters Settings

    ADC input clock frequencies are and 1 MHz. available. Refer to the related information for more details about the sampling rate and the required settling time. Altera Modular ADC and Altera Modular Dual ADC IP Cores References Altera Corporation Send Feedback...
  • Page 47 Parameter Allowed Values Description Use Channel 0 (Dedicated • On Enables the dedicated analog input pin. analog input pin - • Off ANAIN) (CH0 tab) Altera Modular ADC and Altera Modular Dual ADC IP Cores References Altera Corporation Send Feedback...
  • Page 48 This option is available only if you select the Standard sequencer with Avalon-MM sample storage and (Each channel in its own tab, including channel 0) threshold violation detection core variant. Altera Modular ADC and Altera Modular Dual ADC IP Cores References Altera Corporation Send Feedback...
  • Page 49 2-13 Configuration 4: ADC Control Core Only • on page 2-13 Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping • on page 5-6 Altera Modular ADC and Altera Modular Dual ADC IP Cores References...

  • Page 50: Altera Modular Adc Ip Core Channel Name To Max 10 Device Pin Name Mapping

    Provides more information about the sampling rate and settling time. Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping Each ADC channel in the Altera Modular ADC IP core corresponds to different device pin name for single and dual ADC devices.
  • Page 51 UG-M10ADC Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name... 2016.05.02 Table 5-5: Altera Modular ADC IP Core Channel to Pin Mapping for Dual ADC Devices ADC Block Channel Name Pin Name ANAIN1 ADC1IN1 ADC1IN2 ADC1IN3...

  • Page 52: Altera Modular Dual Adc Parameters Settings

    Altera Modular Dual ADC clk_in_pll_c0 input signal. For valid ADC sampling rate and input clock frequencies combinations, refer to the related information. Altera Modular ADC and Altera Modular Dual ADC IP Cores References Altera Corporation Send Feedback...
  • Page 53 This option is available for each enabled channel except the TSD if you select Enable user created expected output file. Altera Modular ADC and Altera Modular Dual ADC IP Cores References Altera Corporation Send Feedback...
  • Page 54 This option is available only if you select the Standard (Each channel in its own sequencer with Avalon-MM sample storage and threshold violation detection core variant. tab, including channel 0) Altera Modular ADC and Altera Modular Dual ADC IP Cores References Altera Corporation Send Feedback...
  • Page 55 ADC1, select NULL for the same sequencer slot number in ADC2. Related Information Sequencer Core • on page 2-17 • Configuration 1: Standard Sequencer with Avalon-MM Sample Storage on page 2-10 Altera Modular ADC and Altera Modular Dual ADC IP Cores References Altera Corporation Send Feedback...

  • Page 56: Altera Modular Dual Adc Ip Core Channel Name To Max 10 Device Pin Name Mapping

    Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping Each ADC channel in the Altera Modular Dual ADC IP core corresponds to different device pin name. Table 5-9: Altera Modular Dual ADC IP Core Channel to Pin Mapping...

  • Page 57: Valid Adc Sample Rate And Input Clock Combination

    5-8 Altera Modular ADC and Altera Modular Dual ADC Interface Signals Depending on parameter settings you specify, different signals are available for the Altera Modular ADC or Altera Modular Dual ADC IP core. Command Interface of Altera Modular ADC and Altera Modular Dual ADC The command interface is an Avalon-ST type interface that supports a ready latency of 0.

  • Page 58: Response Interface Of Altera Modular Adc And Altera Modular Dual Adc

    Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping on page 5-6 • Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping on page 5-12 Response Interface of Altera Modular ADC and Altera Modular Dual ADC The response interface is an Avalon-ST type interface that does not support backpressure.

  • Page 59: Threshold Interface Of Altera Modular Adc And Altera Modular Dual Adc

    UG-M10ADC 5-15 Threshold Interface of Altera Modular ADC and Altera Modular Dual ADC 2016.05.02 Signal Width Description (Bit) Indicates the ADC channel to which the ADC sampling data channel corresponds for the current response. • 31:18—not used • 17—temperature sensor •...

  • Page 60: Csr Interface Of Altera Modular Adc And Altera Modular Dual Adc

    Related Information Altera Modular ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping • on page 5-6 Altera Modular Dual ADC IP Core Channel Name to MAX 10 Device Pin Name Mapping • on page 5-12 CSR Interface of Altera Modular ADC and Altera Modular Dual ADC The CSR interface is an Avalon-MM slave interface.

  • Page 61: Peripheral Clock Interface Of Altera Modular Adc And Altera Modular Dual Adc

    Single reset source that that resets all Altera Modular ADC or reset_n Altera Modular Dual ADC micro cores. ADC PLL Clock Interface of Altera Modular ADC and Altera Modular Dual ADC The ADC PLL clock interface is a clock sink interface type. Table 5-18: ADC PLL Clock Interface Signals...

  • Page 62: Adc Pll Locked Interface Of Altera Modular Adc And Altera Modular Dual Adc

    Parameters Settings for Generating ALTPLL IP Core • on page 4-3 Altera Modular ADC Register Definitions The registers in the generated Altera Modular ADC IP core provide the IP core with the control and settings during operation. Sequencer Core Registers Table 5-20: Command Register (CMD)

  • Page 63: Sample Storage Core Registers

    Read — Reserved 11:0 Sample Read The data sampled by the ADC for Sampled data the corresponding slot. Table 5-22: ADC Sample Register (ADC_SAMPLE) of Altera Modular Dual ADC Address Offset: (slot 63)— (slot 0) 0x3F Name Attribute Description Value...

  • Page 64: Adc Hal Device Driver For Nios Ii Gen 2

    2-18 ADC HAL Device Driver for Nios II Gen 2 The Altera Modular ADC IP core provides a HAL device driver. You can integrate the device driver into the HAL system library for Nios II Gen 2 systems.

  • Page 65: Max 10 Analog To Digital Converter User Guide Archives

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 66: Document Revision History For Max 10 Analog To Digital Converter User Guide

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 67 • Removed statements about availability of the threshold trigger feature in a future version of the Quartus Prime software. The feature is now available from version 15.0 of the software. Document Revision History for MAX 10 Analog to Digital Converter User Guide Altera Corporation Send Feedback...
  • Page 68 • Updated the total RC constant values in the table that shows the RC constant and filter values calculation. • Corrected spelling for "prescaler". September 2014 2014.09.22 Initial release. Document Revision History for MAX 10 Analog to Digital Converter User Guide Altera Corporation Send Feedback...

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