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System Memory and Address Mapping
5.1 Memory Subsystem
The DRAM memory subsystem on the AlphaPC 264DP consists of sixteen 200-pin
buffered DIMM slots, which are organized as four arrays of memory. The 21272
chipset supports two 256-bit memory buses (288-bit including ECC) with two arrays
on each bus (see Figure 5–1).
The 72-bit, 100-MHz DIMMs consist of 64 bits of data and 8 bits of ECC, and can
be 32MB, 64MB, 128MB, or 256MB. The minimum configuration (one array popu-
lated with four 32MB DIMMs) is 128MB. The maximum configuation (four arrays
each populated with four 256MB DIMMs) is 4GB.
The memory cycle time is 83 MHz, identical to the 21272 chipset cycle time.
Note:
Although the memory cycle time is 83 MHz, qualified 100-MHz
DIMMs are required.
Figure 5–1 AlphaPC 264DP Memory Subsystem
21264
12 February 1999 – Subject To Change
21272
Data Bus 1
Dchips
Data Bus 0
Pchips
Array 0
Array 2
Array 1
Cchip
Address/Control
System Memory and Address Mapping
Memory Subsystem
Array 3
5
5–1
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