Compaq AlphaPC 264DP Technical Reference Manual page 59

Table 4–1 IDSEL Assignments for PCI Devices (Continued)
Device/PCI Bus Number
Slot 0/Bus 1
Slot 1/Bus 1
Slot 2/Bus 1
4.6.1 PCI0
The PCI0 supports the southbridge chip, three PCI slots, and the SCSI chip.
4.6.1.1 Southbridge Chip
The southbridge provides the bridge between the PCI bus and the Industry Standard
Architecture (ISA) bus. The southbridge incorporates the logic for the following:
•
A PCI interface (master and slave)
•
An ISA interface (master and slave) (see Section 4.8)
•
Enhanced 7-channel DMA controller that supports DMA transfers and scatter-
gather, and data buffers to isolate the PCI bus from the ISA bus
•
An IDE interface, with a maximum cable length of 12 inches
•
A 14-level interrupt controller
•
A 16-bit BIOS timer
•
Three programmable timer counters
•
Non-maskable interrupt (NMI) control logic
•
Decoding and control for utility bus peripheral devices
•
Speaker driver
•
PCI arbitration control (disabled on AlphaPC 264DP). Refer to the Cypress
hyperCache chipset databook for additional information.
4.6.1.2 PCI0 Expansion Slots
Three PCI bus expansion slots are available on PCI0, with support for 64-bit devices.
Note that 3.3 V and +5 V are provided to the appropriate PCI connector pins.
12 February 1999 – Subject To Change
IDSEL Assignment
PCI1_AD18
PCI1_AD19
PCI1_AD20
PCI Devices
Functional Description
4–9