Compaq AlphaPC 264DP Technical Reference Manual page 61

PCI1 Arbitration Scheme
The arbitration for PCI1 is handled by Pchip1. It is a simple round-robin scheme
between slots 0, 1, and 2.
4.7 PCI and System Interrupts
Interrupt logic is implemented in the Cchip and the FPGA. The interrupt lines from
the PCI slots, southbridge chip, and SCSI chip are connected directly to the IRQ
buffers that reside on the TigData bus. They are driven onto the TigData bus by the
encoded TIGADR signals. The AlphaPC 264DP has 34 interrupts that are shown in
Figure 4–4.
All PCI interrupts are combined in the Cchip and driven out onto the TIGbus. There
is also a Cchip error interrupt and an I/O controller error interrupt within the Cchip.
The CPU interrupt assignment, during normal operation, is listed in Table 4–2.
The Cchip Tig controller polls interrupts continuously except when any other TIG-
bus access is requested. The 48 interrupt inputs (34 enabled, 14 reserved) imple-
mented on the AlphaPC 264DP are polled eight at a time by selecting a byte using
tigadr[2:0] and asserting TigIntOE to allow the selected byte to be driven on the
TIGbus. Once all the interrupts are polled, the Cchip drives the irq[3:0] data to the
two CPUs on to tigdata[7:0] and asserts TigIS to strobe it to the flip flop that drives
it into the CPU.
12 February 1999 – Subject To Change
PCI and System Interrupts
Functional Description
4–11