Compaq AlphaPC 264DP Technical Reference Manual page 54

Dchip Functional Overview
4.3 Dchip Functional Overview
This section provides a functional overview of the Dchips and describes the follow-
ing data bus configurations:
•
sysdata bus, between the Dchips and the CPUs
•
memdata bus, between the Dchips and the memory arrays
•
padbus, between the Dchips and the Pchips
The Dchips provide the data path from the 21264 to main memory. Although a mini-
mum of two chips are required for the memory interface using the 21272, eight chips
are used for the interface on the AlphaPC 264DP.
The chips contain the CPU, Pchip, and memory interface data paths, which includes
DMA and PIO queues.
The Dchips interface to the CPU using the sysdata bus. It interfaces with each Pchip
through the 32-bit padbus (communications path between the Pchip and Dchips,
padbus0 to Pchip0 and padbus1 to Pchip1). The Dchips function as the data path for
the CPU, memory, and I/O subsystem, and contain the following data path functions:
•
DMA write data/PIO read data queue
•
DMA read data/PIO write data queue
•
Queues to allow full bandwidth transfers from memory to the CPU
•
Queue to hold old memory data to be merged with the Pchip data for DMA
writes
4.3.1 Sysdata Bus
The sysdata bus, between the Dchips and each CPU, passes 128 bits of data (64 bits
[8 bytes] from each CPU). It is connected as follows:
•
Dchip 0 connects to each of the two byte 0s.
•
Dchip 1 connects to each of the two byte 1s.
•
Dchip 7 connects to each of the two byte 7s.
Note: The bytes correspond to the bytes from CPU0 and CPU1.
Functional Description
4–4
12 February 1999 – Subject To Change