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System Address Mapping
The Gpen4 register, shown in Figure 5–3, reflects the settings of the mainboard's
switchpack 2 (see Figure 2–3).
Figure 5–3 Gpen4 Register
7 6 5 4 3 2 1 0
The Gpen5 register, shown in Figure 5–4, shows the CPU speed and Bcache config-
uration (set by onboard resistors) on the daughtercard containing CPU0.
Figure 5–4 Gpen5 Register
7 6 5 4 3 2 1 0
The Gpen6 register, shown in Figure 5–5, shows the CPU speed and Bcache config-
uration (set by onboard resistors) on the daughtercard containing CPU1.
Figure 5–5 Gpen6 Register
7 6 5 4 3 2 1 0
The feature mask register, shown in Figure 5–6, allows you to set the Cypress chip's
arbiter activity.
Figure 5–6 Feature Mask Register
7 6 5 4 3 2 1 0
RAZ
System Memory and Address Mapping
5–6
FSB
Reserved
Mini-Debugger
21272 sp[2:0]
AlphaBIOS password bypass
cpu0_speed[2:0]
bc0_config[3:0]
cpu0_present_l
cpu1_speed[2:0]
bc1_config[3:0]
cpu1_present_l
Arbiter select.
0
Selects the arbiter that deasserts the Cypress chip's grant
after it claims the transaction.
1
Selects the arbiter that holds the assertion of the Cypress
chip's grant until it has deasserted its request.
12 February 1999 – Subject To Change
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