Compaq AlphaPC 264DP Technical Reference Manual page 73

Table 5–2 TIGbus Address Mapping (Continued)
capbus Physical
[23:21] Address
101 801 28xx xxx0 RO
110 801 30xx x000 RO
801 30xx x040 RW
801 30xx xA00 RW
801 30xx xA40 RW
801 30xx x3C0 RW
801 30xx x5C0 RW
111 801 38xx x000 RO
801 38xx x040 RAZ
801 38xx x080 WO
801 38xx x0C0 WO
801 38xx x100 RW
801 38xx x140 RO
801 38xx x180 RO
801 38xx x1C0 RW
1
These are two separate halt registers.
12 February 1999 – Subject To Change
Access Function
Gpen_4 Con_bit[7:0]
Gpen_5 CPU0_config[7:0] CPU0 configuration register. See
Flash write enable[0]
Reserved
Reserved
CPU[1:0] HaltA
CPU[1:0] HaltB
Gpen_6 CPU1_config[7:0] CPU1 configuration register. See
Reserved
PCI_0_ok[0]
PCI_1_ok[0]
Soft_reset[0]
Tig_PAL_rev[7:0]
Arbiter_rev[7:0]
Feature_mask[7:0]
System Memory and Address Mapping
System Address Mapping
Comment
General configuration register. See
Figure 5–3.
Figure 5–4.
Writing a 1 to this location enables
flash writes.
—
—
1
Writing a 1 to either bit will halt the
specified CPU.
1
Writing a 1 to either bit will halt the
specified CPU.
Figure 5–5.
—
PCI0 self-test register.
PCI1 self-test register.
To set a hardware reset for a short
period of time, first write a 0, then
write a 1 to this location.
Bits [7:5] specify the major revision
(corresponding to the board revi-
sion), [4:0] specify the minor revi-
sion.
Bits [7:5] specify the major revision,
[4:0] specify the minor revision.
See Figure 5–6.
5–5