Table of Contents
Advertisement
Reset and Initialization
Figure 4–5 AlphaPC 264DP Power Distribution
J33
15
−12 V
+5 V
1, 3, 5, 7,
10, 12, 14
−5 V
ISA Conn.
16
J3
12
+12 V
+3.3 V
1, 3, 5, 7,
9, 11, 14,
16, 18, 20
+5VSB
Comm.
Port
24
J4
+5 V
1, 3, 5, 7,
9, 11, 13,
15, 17
dc-to-dc
Converter
4.10 Reset and Initialization
This logic is contained on the daughtercard in a Quicklogic QL12X16BL FPGA.
This controls reset, power OK, SROM test port, and interrupts to the CPU.
The TIGbus FPGA will implement system irq, general configuration registers, and
Motorola synthesizer setup based on CPU speed and 21272 speed. It will also pro-
vide the interface to the flash ROM.
Functional Description
4–16
Spkr
PCI32
Conn.
Conn.
DIMMs
21272
MISC
MISC
+2.2 V
21264
SSRAMs
Integrated
Comm.
Circuits/Clocks
Port
+2.0 V
Linear
Regulator
Termination
Mainboard
Daughtercard
Linear
Termination
Regulator
+1.5 V
SSRAM
RS-232
Fans
I/O
12 February 1999 – Subject To Change
MISC
Fans
Daughter-
card
Conn.
J3
1-8, 91-98
+3.3 V
87-90,
+2.0 V
177-180
+12 V
176
−12 V
86
Advertisement
Table of Contents
