Compaq AlphaPC 264DP Technical Reference Manual page 17

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The Cchip provides the interface from the CPU and main memory, and includes
a general-purpose interface for the flash ROM and interrupts (TIGbus Interface).
One Cchip is used per system.
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The Dchip provides the data path from the CPU to memory and I/O. Two, four,
or eight Dchips can be used in a system configuration. Eight Dchips provide
two 256-bit memory bus interfaces on the AlphaPC 264DP.
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The Pchip provides an interface to the peripheral component interconnect (PCI).
One or two Pchips can be used in a system configuration. Two Pchips can be
used to provide two independent 64-bit PCI buses. AlphaPC 264DP uses two
Pchips to support two 64-bit PCI buses running at 33 MHz.
The chipset includes the majority of functions required to develop a high-perfor-
mance PC or workstation, requiring minimum discrete logic on the module. It pro-
vides flexible and generic functions to allow its use in a wide range of systems.
1.1.3 CPU Daughtercard
The 21264 microprocessor and level 2 cache reside on a separate daughtercard that
plugs into the mainboard. One or two daughtercards can be used in an AlphaPC
264DP system. The daughtercard is a 10-layer printed-circuit board with dimen-
sions of approximately 14.99 cm × 30.48 cm (5.905 in × 12.0 in). The daughtercard
consists of the following:
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21264 CPU
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Synchronous level 2 cache (2MB or 4MB cache, using late-write cache
SSRAMs)
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A linear regulator, providing 3.3 volts to 1.5 volts conversion for SSRAMs
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dc-to-dc converter for 5 volts to 2.2 volts for 21264 core power
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Reset and configuration FPGA
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Presence detect for cache configuration and CPU speed
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512KB flash ROM used as SROM
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SROM test port
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270-pin interface to mainboard (system clock forwarding interface and miscella-
neous signals)
12 February 1999 – Subject To Change
System Components and Features
AlphaPC 264DP Introduction
1–3