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PCI and System Interrupts
Figure 4–4 Interrupt Request Register
63
62 61 60
56
55 54 53 52
Reserved
31
28
27
24 23
A0
B0
C0 D0
A2
B2
A1
B1
C1 D1
Table 4–2 CPU Interrupt Assignment
CPU Interrupt
cpu_irq0
cpu_irq1
cpu_irq2
cpu_irq3
cpu_irq4
cpu_irq5
The ISA bus interrupts (IRQ0 through IRQ8 and IRQ12 through IRQ14) are all
nested through the southbridge (on INT output) to the Cchip (via the TIGbus) and
then into the CPU. The interrupt assignment is configurable but is normally used as
shown in Table 4–3.
Functional Description
4–12
49
48 47
44 43
Reserved
A0
B0
C0 D0
A1
20
19 18 17
16
C2 D2
Interrupt Souce
Pchips
PCI/ISA devices
rtc_irq
c_chip_csr
Halt jumper or software
Reserved
40 39
36
35
B1
C1 D1
A2
B2
C2 D2
Reserved
Reserved
Description
Error interrupts
PCI and ISA interrupts
Real-time clock interrupt
Interprocessor
Halt for each processor
—
12 February 1999 – Subject To Change
32
PCI1_INT x 2
PCI1_INT x 1
PCI1_INT x 0
I2C_IOINT_L
PCI0_NMI
PCI0_SMI_INT
PCI0_INT
PCI1_BUS_ERROR
PCI0_BUS_ERROR
Reserved
00
I2C_INT_L
PCI0_IRQ_ADPTB
PCI0_IRQ_ADPTA
PCI0_INT x 2
PCI0_INT x 1
PCI0_INT x 0
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