Compaq AlphaPC 264DP Technical Reference Manual page 56

Pchip Functional Overview
4.4 Pchip Functional Overview
The Pchip is the bridge between the PCI and the CPU and its cache and memory, and
the chip interface protocol is compliant with the PCI Local Bus Specification, Revi-
sion 2.1. The Pchip contains all control functions of the bridge and some data path
functions. Other data path functions reside in the Dchip.
Two Pchips are used on the AlphaPC 264DP to provide two separate 64-bit PCI
buses.
The Pchip provides all controls and interfaces to the PCI and contains the following
components and functions:
•
Single 64-bit PCI bus implemented at 33 MHz
•
PCI central arbiter (disabled on Pchip0)
•
DMA write buffer
•
Scatter-gather translation lookaside buffer (TLB)
•
Downsteam and upstream queues for address and data
4.4.1 PCI Interface
The PCI interface of the Pchip is a fully compliant PCI host bridge. It acts as a mas-
ter on the PCI on CPU-initiated transactions and is a target on memory space transac-
tions initiated by PCI masters.
The Pchip is not a PCI peripheral; it is a bridge between the PCI peripherals and
memory. The chip implements functions of a host bridge that are not sufficient to
interface the chip as a PCI peripheral component.
Functional Description
4–6
12 February 1999 – Subject To Change