Compaq AlphaPC 264DP Technical Reference Manual page 52

Cchip Functional Overview
4.2 Cchip Functional Overview
The Cchip provides the control interface between the 21264 and 21272 chipset. In
addition, it provides control for the Dchips and Pchips. It also controls the memory
subsystem and TIGbus. The Cchip performs the following functions:
•
Maintains queues to store addresses and commands
•
Controls and moves data to and from arrays of main memory
•
Responds to commands from the CPU
•
Supports interrupts and flash ROM via the TIGbus
On the AlphaPC 264DP, the Cchip controls four arrays of SDRAM DIMMs. The
DIMMs can range in size from 32MB to 256MB. Note that there are two separate
256-bit paths and four arrays (two on each bus) on the AlphaPC 264DP.
The components of the memory subsystem are distributed between the Cchip and the
Dchips. Together, the chips serve as an interface between the CPU and memory
subsystem (see Figure 4–1).
The following list summarizes the major features of the Cchip:
•
Accepts requests from the Pchip and CPU
•
Orders the arriving requests
•
Selects the request and issues controls to the DRAMs
•
Issues probes to the CPU for the selected requests
•
Translates CPU PIO address to PCI and CSR addresses
•
Issues commands to the Pchip for the selected request
•
Issues responses to the Dchip for the DRAM accesses, the probe, and Pchip
responses
•
Controls the TIGbus to manage interrupts and maintains CSRs, including those
that represent interrupt status
4.2.1 CPU Interface
The CPU and Cchip communicate with each other through the system port. The sys-
tem port is made up of unidirectional address and command buses. The Cchip system
interface logic decodes the sysPort address for both CPU and DMA requests to
determine the action to take. It supports cacheable memory accesses, programmed
I/O, interrupts, Tig addresses, as well as accesses to 21272 CSR space.
Functional Description
4–2
12 February 1999 – Subject To Change