Dat3 - Analog Devices AD9874 Manual

reference source can be made by installing R7 or R8. Note, the
crystal oscillator is locally decoupled and its supply tied to TB3
(VDIRECT).
FPGA, FIFO, and NIDAQ Interface (See Figures 6c and 6d)
The AD9874 evaluation board is designed to interface to a PC via
a National Instruments NI 6533 (or NI6534) series digital IO
(NIDAQ) card. The evaluation software that configures the
AD9874 and analyzes its output data supports this interface. A
XILINX FPGA (U3) and IDT FIFO (U11) are used to format
the AD9874's serial output data and to control the interface
between the AD9874 and NIDAQ card as shown in Figure 1. The
interface supports normal data output modes of operation in
which decimated 16- or 24-bit I and Q data (along with optional
embedded AGC data) are provided within a frame. It also sup-
ports a mode that provides the undecimated digital output from
the AD9874's - ADC.
For normal output data modes, the FPGA formats the AD9874's
serial output (SSI) data within a frame into 16-bit parallel data
for the FIFO and controls the interface timing between the FIFO
and NIDAQ card. Line drivers (U12 and U13) are included to
drive the NIDAQ card via a shielded cable (not included) with
the 16-bit data. In the special interface mode, the FPGA provides
the buffered undecimated output data directly to the NIDAQ
card at the CLK rate.
The FPGA is also used to control the serial port interface (SPI)
between the AD9874 and NIDAQ card. In this case, the FPGA
buffers and conditions the 5 V logic input levels from the NIDAQ
card. It also contains a bidirectional buffer that is used to con-
PE
PC
PD
AD9874
FS
CLKOUT
DOUTB
DOUTA
SYNCB
DOUTB
DOUT
DOUTA
RESET_
FROM SW1 ON BOARD
Figure 1. Block Diagram of XILINX FPGA and FIFO Used to Control Interface between AD9874 and NIDAQ Card
REV. 0
XILINX FPGA
SPI_ADDR
SPI_DATA
SPI
CONFIGURATION
DECODER
R_W_BIT
(MODE.V)
DW
DR48
SSI
SERIAL-TO-PARALLEL
CONVERTER
(DOUTS 2P.V)
16
trol the data flow for SPI WRITE and READ operations. The
FPGA is programmed via a serial EPROM (U4). A green LED
illuminates when the FPGA is configured.
The evaluation board comes installed with a 68-lead male SCS1-11
type cable connector. The user is required to purchase a
SH68-68-D1 shielded interface cable (National Instruments Part
No. 183432-01) and NI 6533 digital I/O card (www.ni.com/pdf/
products/us/2mhw332-333e.pdf).
Interfacing AD9874 Evaluation Board to a DSP (See Figure 6c)
The current AD9874 evaluation board unfortunately does not
provide a simple and clean interface to a DSP evaluation board.
However, only a minor board modification is required to enable
such an interface. The SSI digital output interface is simple
since the AD9874's output signals are buffered by the FPGA
and made available from header J4. Note, the DGND test point
next to J4 should be used to provide a digital ground return path
between the two evaluation boards. The SPI interface is more
complicated since there is no header provided for the PE, PC,
and PD signals. The solution is to use the PE, PC, and PD test
points located next to the FPGA and lift the corresponding
FPGA pins (Pins 19, 20, and 21 of U3). These FPGA pins
provide buffered output signals and can be disconnected to
prevent bus contention.
Power Supply Interface (See Figure 6e and 6f)
The AD9874 evaluation board contains four power supply
terminal blocks (TB) for external power supply connections.
TB3 allows the user to directly apply power to any individual
DC
LEVEL
SHIFTER
6
R_W_BIT
SPT
SERIAL-TO-PARALLEL
8
CONVERTER
(SPI.V)
FIFO WRITE CLK GENERATOR
(WR_CLK.V)
FIFO_WR_EN
FIFO CONTROLLER
(FIFOCNT.V)
DOUTA
DOUTB
DOUT
FIFO_DATA
LINE
FIFO
16
DRIVERS
–3–
EVAL-AD9874EB
PE_5V
PD_IN_5V
PD_OUT_3V
PC_5V
MRSCTR_
J4
FS_BUFF
CLKOUT_BUFF
DOUTA_BUFF
DOUTB_BUFF
DOUT_BUFF
FIFO_DATA_BUFF
16